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IDT5T907 Datasheet, PDF (1/17 Pages) Integrated Device Technology – 2.5V SINGLE DATA RATE 1:10 CLOCK BUFFER TERABUFFER | |||
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IDT5T907
2.5V SINGLE DATA RATE 1:10 CLOCK BUFFER TERABUFFER
2.5V SINGLE DATA RATE
1:10 CLOCK BUFFER
TERABUFFERâ¢
INDUSTRIAL TEMPERATURE RANGE
IDT5T907
FEATURES:
⢠Guaranteed Low Skew < 25ps (max)
⢠Very low duty cycle distortion
⢠High speed propagation delay < 2.5ns. (max)
⢠Up to 250MHz operation
⢠Very low CMOS power levels
⢠1.5V VDDQ for HSTL interface
⢠Hot insertable and over-voltage tolerant inputs
⢠3-level inputs for selectable interface
⢠Selectable HSTL, eHSTL, 1.8V / 2.5V LVTTL, or LVEPECL input
interface
⢠Selectable differential or single-ended inputs and ten single-
ended outputs
⢠2.5V VDD
⢠Available in TSSOP package
APPLICATIONS:
⢠Clock and signal distribution
DESCRIPTION:
The IDT5T907 2.5V single data rate (SDR) clock buffer is a user-selectable
single-ended or differential input to ten single-ended outputs buffer built on
advanced metal CMOS technology. The SDR clock buffer fanout from a single
or differential input to ten single-ended outputs reduces the loading on the
preceding driver and provides an efficient clock distribution network. The
IDT5T907 can act as a translator from a differential HSTL, eHSTL, 1.8V/2.5V
LVTTL, LVEPECL, or single-ended 1.8V/2.5V LVTTL input to HSTL, eHSTL,
1.8V/2.5V LVTTL outputs. Selectable interface is controlled by 3-level input
signals that may be hard-wired to appropriate high-mid-low levels.
The IDT5T907 has two output banks that can be asynchronously enabled/
disabled. Multiple power and grounds reduce noise.
FUNCTIONAL BLOCK DIAGRAM
TxS
GL
G1
OUTPUT
CONTROL
Q1
OUTPUT
CONTROL
Q2
RxS
A
A/VREF
G2
OUTPUT
CONTROL
Q3
OUTPUT
CONTROL
Q4
OUTPUT
CONTROL
Q5
OUTPUT
CONTROL
Q6
OUTPUT
CONTROL
Q7
OUTPUT
CONTROL
Q8
OUTPUT
CONTROL
Q9
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
© 2003 Integrated Device Technology, Inc.
OUTPUT
CONTROL
1
Q10
FEBRUARY 2003
DSC-5899/22
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