IDT5T905 Datasheet, PDF (1/17 Pages) Integrated Device Technology – 2.5V SINGLE DATA RATE 1:5 CLOCK BUFFER TERABUFFER

IDT5T905
2.5V SINGLE DATA RATE 1:5 CLOCK BUFFER TERABUFFER
2.5V SINGLE DATA RATE
1:5 CLOCK BUFFER
TERABUFFER™
INDUSTRIAL TEMPERATURE RANGE
IDT5T905
FEATURES:
• Guaranteed Low Skew < 25ps (max)
• Very low duty cycle distortion
• High speed propagation delay < 2.5ns. (max)
• Up to 250MHz operation
• Very low CMOS power levels
• 1.5V VDDQ for HSTL interface
• Hot insertable and over-voltage tolerant inputs
• 3-level inputs for selectable interface
• Selectable HSTL, eHSTL, 1.8V / 2.5V LVTTL, or LVEPECL input
interface
• Selectable differential or single-ended inputs and five single-
ended outputs
• 2.5V VDD
• Available in TSSOP package
APPLICATIONS:
• Clock and signal distribution
FUNCTIONAL BLOCK DIAGRAM
DESCRIPTION:
The IDT5T905 2.5V single data rate (SDR) clock buffer is a user-selectable
single-ended or differential input to five single-ended outputs buffer built on
advanced metal CMOS technology. The SDR clock buffer fanout from a single
or differential input to five single-ended outputs reduces the loading on the
preceding driver and provides an efficient clock distribution network. The
IDT5T905 can act as a translator from a differential HSTL, eHSTL, 1.8V/2.5V
LVTTL, LVEPECL, or single-ended 1.8V/2.5V LVTTL input to HSTL, eHSTL,
1.8V/2.5V LVTTL outputs. Selectable interface is controlled by 3-level input
signals that may be hard-wired to appropriate high-mid-low levels. Multiple
power and grounds reduce noise.
TxS
GL
G
OUTPUT
CONTROL
Q1
RxS
A
A/VREF
OUTPUT
CONTROL
Q2
OUTPUT
CONTROL
Q3
OUTPUT
CONTROL
Q4
OUTPUT
CONTROL
Q5
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
1
© 2003 Integrated Device Technology, Inc.
FEBRUARY 2003
DSC-5942/25