IDT5T2110 Datasheet, PDF (1/23 Pages) Integrated Device Technology – 2.5V ZERO DELAY PLL DIFFERENTIAL CLOCK DRIVER TERACLOCK

IDT5T2110
2.5V ZERO DELAY PLL DIFFERENTIAL CLOCK DRIVER TERACLOCK
2.5V ZERO DELAY PLL
DIFFERENTIAL CLOCK
DRIVER TERACLOCK™
INDUSTRIAL TEMPERATURE RANGE
IDT5T2110
FEATURES:
• 2.5 VDD
• 6 differential outputs
• Low skew: 100ps all outputs
• Selectable positive or negative edge synchronization
• Tolerant of spread spectrum input clock
• Synchronous output enable
• Selectable inputs
• Input frequency: 4.17MHz to 250MHz
• Output frequency: 12.5MHz to 250MHz
• 1.8V / 2.5V LVTTL: up to 250MHz
• HSTL / eHSTL: up to 250MHz
• Hot insertable and over-voltage tolerant inputs
• 3-level inputs for selectable interface
• 3-level inputs for feedback divide selection with multiply ratios
of(1-6, 8, 10, 12)
• Selectable HSTL, eHSTL, 1.8V/2.5V LVTTL, or LVEPECL input
interface
• Selectable differential or single-ended inputs and six differen-
tial outputs
• PLL bypass for DC testing
• External differential feedback, internal loop filter
• Low Jitter: <75ps cycle-to-cycle
• Power-down mode
• Lock indicator
• Available in BGA and VFQFPN package
FUNCTIONAL BLOCK DIAGRAM
DESCRIPTION:
The IDT5T2110 is a 2.5V PLL differential clock driver intended for high
performance computing and data-communications applications. The
IDT5T2110 has six differential outputs in six banks, including a dedicated
differential feedback. The redundant input capability allows for a smooth
change over to a secondary clock source when the primary clock source
is absent.
The feedback bank allows divide-by-functionality from 1 to 12 through
the use of the DS[1:0] inputs. This provides the user with frequency
multiplication 1 to 12 without using divided outputs for feedback. Each output
bank also allows for a divide-by functionality of 2 or 4.
The 5T2110 features a user-selectable, single-ended or differential input to
six differential outputs. The differential clock driver also acts as a translator from
a differential HSTL, eHSTL, 1.8V/2.5V LVTTL, LVEPECL, or single-ended
1.8V/2.5V LVTTL input to HSTL, eHSTL, or 1.8V/2.5V LVTTL outputs.
Selectable interface is controlled by 3-level input signals that may be hard-wired
to appropriate high-mid-low levels. The differential outputs can be synchro-
nously enabled/disabled.
Furthermore, when PE is held high, all the outputs are synchronized with
the positive edge of the REF clock input. When PE is held low, all the outputs
are synchronized with the negative edge of REF.
TxS
OMODE
FB
FB/
VREF2
REF0
REF0/
VREF0
RxS
REF1
REF1/
VREF1
/N
33
DS1:0
0
1
REF_SEL
PD PE FS LOCK
PLL
PLL_EN
0
1
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
1
c 2004 Integrated Device Technology, Inc.
1sOE
Divide
Select
1F2:1
2sOE
Divide
Select
2F2:1 3sOE
Divide
Select
3F2:1 _4sOE
Divide
Select
4F2:1
Divide
Select
5sOE
5F2:1
Divide
Select
FBF2:1
1Q
1Q
2Q
2Q
3Q
3Q
4Q
4Q
5Q
5Q
QFB
QFB
MAY 2003
DSC 5982/25