IDT5T2010 Datasheet, PDF (1/23 Pages) Integrated Device Technology – 2.5V ZERO DELAY PLL CLOCK DRIVER TERACLOCK

IDT5T2010
2.5V ZERO DELAY PLL CLOCK DRIVER TERACLOCK
INDUSTRIAL TEMPERATURE RANGE
2.5V ZERO DELAY PLL
CLOCK DRIVER TERACLOCK™
IDT5T2010
FEATURES:
• 2.5 VDD
• 5 pairs of outputs
• Low skew: 50ps same pair, 100ps all outputs
• Selectable positive or negative edge synchronization
• Tolerant of spread spectrum input clock
• Synchronous output enable
• Selectable inputs
• Input frequency: 4.17MHz to 250MHz
• Output frequency: 12.5MHz to 250MHz
• 1.8V / 2.5V LVTTL: up to 250MHz
• HSTL / eHSTL: up to 250MHz
• Hot insertable and over-voltage tolerant inputs
• 3-level inputs for selectable interface
• 3-level inputs for feedback divide selection with multiply ratios
of(1-6, 8, 10, 12)
• Selectable HSTL, eHSTL, 1.8V/2.5V LVTTL, or LVEPECL input
interface
• Selectable differential or single-ended inputs and ten single-
ended outputs
• PLL bypass for DC testing
• External differential feedback, internal loop filter
• Low Jitter: <75ps cycle-to-cycle
• Power-down mode
• Lock indicator
• Available in BGA and VFQFPN packages
FUNCTIONAL BLOCK DIAGRAM
DESCRIPTION:
The IDT5T2010 is a 2.5V PLL clock driver intended for high perfor-
mance computing and data-communications applications. The IDT5T2010
has ten outputs in five banks of two, plus a dedicated differential feedback.
The redundant input capability allows for a smooth change over to a
secondary clock source when the primary clock source is absent.
The feedback bank allows divide-by-functionality from 1 to 12 through
the use of the DS[1:0] inputs. This provides the user with frequency
multiplication 1 to 12 without using divided outputs for feedback. Each output
bank also allows for a divide-by functionality of 2 or 4.
The IDT5T2010 features a user-selectable, single-ended or differential
input to ten single-ended outputs. The clock driver also acts as a translator from
a differential HSTL, eHSTL, 1.8V/2.5V LVTTL, LVEPECL, or single-ended
1.8V/2.5V LVTTL input to HSTL, eHSTL, or 1.8V/2.5V LVTTL outputs.
Selectable interface is controlled by 3-level input signals that may be hard-wired
to appropriate high-mid-low levels. The outputs can be synchronously
enabled/disabled.
Furthermore, when PE is held high, all the outputs are synchronized with
the positive edge of the REF clock input. When PE is held low, all the outputs
are synchronized with the negative edge of REF.
TxS
OMODE
1sOE
Divide
1Q0
Select
1Q1
1F2:1
2sOE
FB
FB/
VREF2
REF0
PD PE FS LOCK
Divide
2Q0
Select
PLL_EN
2Q1
/N
33
2F2:1
3sOE
DS1:0
PLL
Divide
3Q0
Select
0
3Q1
REF0/
VREF0
0
RxS
1
3F2:1
4sOE
1
Divide
4Q0
Select
4Q1
REF1
REF1/
VREF1
REF_SEL
4F2:1
5sOE
Divide
5Q0
Select
5Q1
5F2:1
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
1
c 2004 Integrated Device Technology, Inc.
Divide
Select
FBF2:1
QFB
QFB
MAY 2003
DSC 5981/24