IDT5992A Datasheet, PDF (1/8 Pages) Integrated Device Technology – PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK-TM

IDT5992A
PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
PROGRAMMABLE SKEW
PLL CLOCK DRIVER
TURBOCLOCK™
IDT5992A
FEATURES:
• 4 pairs of programmable skew outputs
• Low skew: 200ps same pair, 250ps all outputs
• Selectable positive or negative edge synchronization:
Excellent for DSP applications
• Synchronous output enable
• Output frequency: 3.75MHz to 100MHz
• 2x, 4x, 1/2, and 1/4 outputs
• 5V with CMOS outputs
• 3 skew grades:
IDT5992A-2: tSKEW0<250ps
IDT5992A-5: tSKEW0<500ps
IDT5992A-7: tSKEW0<750ps
• 3-level inputs for skew and PLL range control
• PLL bypass for DC testing
• External feedback, internal loop filter
• 46mA IOL high drive outputs
• Low Jitter: <200ps peak-to-peak
• Outputs drive 50Ω terminated lines
• Pin-compatible with Cypress CY7B992
• Available in PLCC Package
DESCRIPTION:
The IDT5992A is a high fanout PLL based clock driver intended for
high performance computing and data-communications applications. A
key feature of the programmable skew is the ability of outputs to lead or
lag the REF input signal. The IDT5992A has eight programmable skew
outputs in four banks of 2. Skew is controlled by 3-level input signals
that may be hard-wired to appropriate HIGH-MID-LOW levels.
The IDT5992A maintains Cypress CY7B992 compatibility while pro-
viding two additional features: Synchronous Output Enable (GND/sOE),
and Positive/Negative Edge Synchronization (VDDQ/PE). When the GND/
sOE pin is held low, all the outputs are synchronously enabled (CY7B992
compatibility). However, if GND/sOE is held high, all the outputs except
3Q0 and 3Q1 are synchronously disabled.
Furthermore, when the VDDQ/PE is held high, all the outputs are syn-
chronized with the positive edge of the REF clock input (CY7B992 com-
patibility). When VDDQ/PE is held low, all the outputs are synchronized
with the negative edge of REF.
FUNCTIONAL BLOCK DIAGRAM
G N D /sO E
V DDQ /P E
REF
FB
PLL
3
FS
Skew
S e le ct
3
3
1 F 1 :0
Skew
S e le ct
3
3
2 F 1 :0
Skew
S e le ct
3
3
3 F 1 :0
Skew
S e le ct
3
3
4 F 1 :0
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL
c 2001 Integrated Device Technology, Inc.
TEMPERATURE
1
RANGES
1Q0
1Q1
2Q0
2Q1
3Q0
3Q1
4Q0
4Q1
AUGUST 2001
DSC 5391/1