IDT59920A Datasheet, PDF (1/6 Pages) Integrated Device Technology – LOW SKEW PLL CLOCK DRIVER TURBOCLOCK JR.

IDT59920A
LOW SKEW PLL CLOCK DRIVER TURBOCLOCK JR.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
LOW SKEW
PLL CLOCK DRIVER
TURBOCLOCK™ JR.
IDT59920A
FEATURES:
• Eight zero delay outputs
• Selectable positive or negative edge synchronization
• Synchronous output enable
• Output frequency: 15MHz to 100MHz
• CMOS outputs
• 3 skew grades:
IDT59920A-2: tSKEW0<250ps
IDT59920A-5: tSKEW0<500ps
IDT59920A-7: tSKEW0<750ps
• 3-level inputs for PLL range control
• PLL bypass for DC testing
• External feedback, internal loop filter
• 46mA IOL high drive outputs
• Low Jitter: <200ps peak-to-peak
• Outputs drive 50Ω terminated lines
• Pin-compatible with Cypress CY7B9920
• Available in SOIC package
FUNCTIONAL BLOCK DIAGRAM
DESCRIPTION:
The IDT59920A is a high fanout phase lock loop clock driver in-
tended for high performance computing and data-communications appli-
cations. The IDT59920A has CMOS outputs.
The IDT59920A maintains Cypress CY7B9920 compatibility while
providing two additional features: Synchronous Output Enable (GND/
sOE), and Positive/Negative Edge Synchronization (VDDQ/PE). When
the GND/sOE pin is held low, all outputs are synchronously enabled
(CY7B9920 compatibility). However, if GND/sOE is held high, all out-
puts except Q2 and Q3 are synchronously disabled.
Furthermore, when the VDDQ/PE is held high, all outputs are synchro-
nized with the positive edge of the REF clock input (CY7B9920 compat-
ibility). When VDDQ/PE is held low, all outputs are synchronized with the
negative edge of REF.
The FB signal is compared with the input REF signal at the phase
detector in order to drive the VCO. Phase differences cause the VCO of
the PLL to adjust upwards or downwards accordingly.
An internal loop filter moderates the response of the VCO to the
phase detector. The loop filter transfer function has been chosen to
provide minimal jitter (or frequency variation) while still providing accu-
rate responses to input frequency changes.
VDDQ/PE
G N D /sO E
Q0
Q1
Q2
FB
Q3
PLL
REF
Q4
Q5
FS
Q6
Q7
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL
c 2001 Integrated Device Technology, Inc.
TEMPERATURE
1
RANGES
SEPTEMBER 2001
DSC 5846/2