ICS9LPR502 Datasheet, PDF (1/29 Pages) Integrated Device Technology – 56-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR

Datasheet
56-PIN CK505 W/FULLY INTEGRATED VOLTAGE
REGULATOR
ICS9LPR502
Recommended Application:
CK505 compliant clock with fully integrated voltage
regulator, PCIe Gen 1 compliant
Output Features:
• 2 - CPU differential low power push-pull pairs
• 7 - SRC differential low power push-pull pairs
• 1 - CPU/SRC selectable differential low power push-pull
pair
• 1 - SRC/DOT selectable differential low power push-pull
pair
• 5 - PCI, 33MHz
• 1 - PCI_F, 33MHz free running
• 1 - USB, 48MHz
• 1 - REF, 14.318MHz
Key Specifications:
• CPU outputs cycle-cycle jitter < 85ps
• SRC output cycle-cycle jitter < 125ps
• PCI outputs cycle-cycle jitter < 250ps
• +/- 100ppm frequency accuracy on CPU & SRC
clocks
Features/Benefits:
• Does not require external pass transistor for voltage
regulator
• Supports spread spectrum modulation, default is 0.5%
down spread
• Uses external 14.318MHz crystal, external crystal
load caps are required for frequency tuning
• One differential push-pull pair selectable between
SRC and two single-ended outputs
Table 1: CPU Frequency Select Table
FSLC² FSLB¹ FSLA¹
B0b7 B0b6 B0b5
CPU
MHz
SRC
MHz
PCI REF USB
MHz MHz MHz
0
0
0
266.66
0
0
1
133.33
0
1
0
200.00
0
1
1
166.66 100.00 33.33 14.318 48.00
1
0
0
333.33
1
0
1
100.00
1
1
0
400.00
1
1
1
Reserved
1. FS_LA and FS_LB are low-threshold inputs.Please see V_{IL_FS} and V_{IH_FS} specifications in
the Input/Supply/Common Output Parameters Table for correct values.
Also refer to the Test Clarification Table.
2. FS_LC is a three-level input. Please see the V_{IL_FS} and V_{IH_FS}
specifications in the Input/Supply/Common Output Parameters Table for correct values.
IDT^TM/ICS^TM 56-pin CK505 w/Fully Integrated Voltage Regulator
Pin Configuration
DOT
MHz
96.00
PCI0/CR#_A 1
VDDPCI 2
PCI1/CR#_B 3
PCI2/TME 4
PCI3 5
56 SCLK
55 SDATA
54 REF0/FSLC/TEST_SEL
53 VDDREF
52 X1
PCI4/SRC5_EN 6
PCI_F5/ITP_EN 7
GNDPCI 8
VDD48 9
USB_48MHz/FSLA 10
GND48 11
VDDI/O96Mhz 12
DOTT_96/SRCT0 13
DOTC_96/SRCC0 14
GND 15
VDD 16
SRCT1/SE1 17
SRCC1/SE2 18
GND 19
VDDPLL3I/O 20
SRCT2/SATAT 21
SRCC2/SATAC 22
GNDSRC 23
SRCT3/CR#_C 24
SRCC3/CR#_D 25
VDDSRCI/O 26
SRCT4 27
SRCC4 28
51 X2
50 GNDREF
49 FSLB/TEST_MODE
48 CK_PWRGD/PD#
47 VDDCPU
46 CPUT0
45 CPUC0
44 GNDCPU
43 CPUT1
42 CPUC1
41 VDDI/OCPU
40 NC
39 CPUT2_ITP/SRCT8
38 CPUC2_ITP/SRCC8
37 VDDSRCI/O
36 SRCT7/CR#_F
35 SRCC7/CR#_E
34 GNDSRC
33 SRCT6
32 SRCC6
31 VDDSRC
30 PCI_STOP#/SRCT5
29 CPU_STOP#/SRCC5
56-SSOP/TSSOP
1124D—02/26/09
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