ICS97ULP844A Datasheet, PDF (1/12 Pages) Integrated Circuit Systems – 1.8V Low-Power Wide-Range Frequency Clock Driver

Integrated
Circuit
Systems, Inc.
ICS97UL P 8 44A
1.8V Low-Power Wide-Range Frequency Clock Driver
Recommended Application:
• DDR2 Memory Modules / Zero Delay Board Fan Out
• Provides complete DDR DIMM logic solution with
ICSSSTU32864/SSTUF32864/SSTUF32866
Product Description/Features:
• Low skew, low jitter PLL clock driver
• 1 to 4 differential clock distribution (SSTL_18)
• Feedback pins for input to output synchronization
• Spread Spectrum tolerant inputs
• Auto PD when input signal is at a certain logic state
Switching Characteristics:
• Period jitter: 40ps
• Half-period jitter: 60ps
• CYCLE - CYCLE jitter 40ps
• OUTPUT - OUTPUT skew: 40ps
Pin Configuration
12 3 4 5
A
B
C
D
E
F
28-Ball BGA
Top View
Block Diagram
OE
OS
AV_DD
Powerdown
Control and
Test Logic
LD* or OE
LD*
PLL bypass
CLK_INT
CLK_INC
10K-100k
PLL
GND
FB_INT
FB_INC
* The Logic Detect (LD) powers down the device when a
logic low is applied to both CLK_INT and CLK_INC.
1110A—05/16/05
CLKT0
CLKC0
CLKT1
CLKC1
CLKT2
CLKC2
CLKT3
CLKC3
Ball Assignments
1
2
3
4
A
CLKT0
CLKC0
CLKC1
CLKT1
5
FB_INT
B CK_INT
VDD
NB
VDD
FB_INC
C CK_INC
OE
VDD
OS
FB_OUTC
D
AGND
GND
V_DD
GND FB_OUTT
E
AVDD
GND
NB
GND
GND
F CLKC3
CLKT3
CLKC2
CLKT2
GND
FB_OUTT
FB_OUTC