ICS889832 Datasheet, PDF (1/15 Pages) Integrated Device Technology – LOW SKEW, 1-TO-4 DIFFERENTIAL-TOLVDS FANOUT BUFFER

LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-
LVDS FANOUT BUFFER
GENERAL DESCRIPTION
The ICS889832 is a high speed 1-to-4 Differential-
ICS
to-LVDS Fanout Buffer and is a member of the
HiPerClockS™ _{HiPerClockS™ family of high performance clock}
solutions from IDT. The ICS889832 is optimized
for high speed and very low output skew, making
it suitable for use in demanding applications such as SONET,
1 Gigabit and 10 Gigabit Ethernet, and Fibre Channel. The
internally terminated differential input and VREF_AC pin allow
other differential signal families such as LVPECL, LVDS, and
SSTL to be easily interfaced to the input with minimal use of
external components. The device also has an output enable
pin which may be useful for system test and debug purposes.
The ICS889832 is packaged in a small 3mm x 3mm 16-pin
VFQFN package which makes it ideal for use in space-
constrained applications.
ICS889832
FEATURES
• Four differential LVDS outputs
• IN, nIN pair can accept the following differential input levels:
LVPECL, LVDS, SSTL
•
50Ω
internal
input
termination
to
V
T
• Output frequency: >2GHz
• Output skew: 25ps (maximum)
• Part-to-part skew: 200ps (maximum)
• Additive phase jitter, RMS: <0.2ps (typical)
• Propagation delay: 510ps (maximum)
• 2.5V operating supply
• -40°C to 85°C ambient operating temperature
• Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
BLOCK DIAGRAM
IN
50Ω
V_T
50Ω
nIN
V_{REF_AC}
EN
DQ
PIN ASSIGNMENT
16 15 14 13
Q0
Q1 1
12 IN
nQ0
nQ1 2
11 VT
Q2 3
10 VREF_AC
Q1
nQ2 4
9 nIN
5678
nQ1
Q2
ICS889832
nQ2
16-Lead VFQFN
3mm x 3mm x 0.95 package body
Q3
K Package
Top View
nQ3
IDT^™ / ICS^™ LVDS FANOUT BUFFER
1
ICS889832AK REV A SEPTEMBER 19, 2006