ICS853S011CI Datasheet, PDF (1/19 Pages) Integrated Device Technology – Maximum output frequency

Low Skew, 1-to-2, Differential-to-2.5V, 3.3V ICS853S011CI
LVPECL/ECL Fanout Buffer
DATA SHEET
General Description
The ICS853S011CI is a low skew, high performance 1-to-2
Differential-to-2.5V/3.3V LVPECL/ECL Fanout Buffer. The
ICS853S011CI is characterized to operate from either a 2.5V or a
3.3V power supply. Guaranteed output and part-to-part skew
characteristics make the ICS853S011CI ideal for those clock
distribution applications demanding well defined performance and
repeatability.
Features
• Two differential 2.5V, 3.3V LVPECL/ECL outputs
• One differential PCLK, nPCLK input pair
• PCLK, nPCLK pairs can accept the following
differential input levels: LVPECL, LVDS, CML, SSTL
• Maximum output frequency: >2.5GHz
• Translates any single-ended input signal to 3.3V LVPECL levels
with resistor bias on nPCLK input
• Output skew: 20ps (maximum)
• Part-to-part skew: 150ps (maximum)
• Propagation delay: 330ps (maximum)
• LVPECL mode operating voltage supply range:
V_CC = 2.375V to 3.8V, V_EE = 0V
• ECL mode operating voltage supply range:
V_CC = 0V, V_EE = -3.8V to -2.375V
• -40°C to 85°C ambient operating temperature
• Lead-free (RoHS 6) packaging
Block Diagram
PCLK ^Pulldown
nPCLK ^{Pullup/Pulldown}
Q0
nQ0
Q1
nQ1
ICS853S011CGI REVISION A JULY 16, 2013
Pin Assignment
Q0 1
nQ0 2
Q1 3
nQ1 4
8 VCC
7 PCLK
6 nPCLK
5 VEE
ICS853S011CI
8-Lead SOIC, 150MIL
3.90mm x 4.90mm x 1.37mm package body
M Package
Top View
8-Lead TSSOP, 118MIL
3.0mm x 3.0mm x 0.97mm package body
G Package
Top View
1
©2013 Integrated Device Technology, Inc.