ICS8524 Datasheet, PDF (1/17 Pages) Integrated Circuit Systems – LOW SKEW, 1-TO-22 DIFFERENTIAL-TO-HSTL FANOUT BUFFER

ICS8524
LOW SKEW, 1-TO-22
DIFFERENTIAL-TO-HSTL FANOUT BUFFER
GENERAL DESCRIPTION
ICS
The ICS8524 is a low skew, 1-to-22 Differential-
to-HSTL Fanout Buffer and a member of the
HiPerClockS™ _{HiPerClockS™Family of High Performance Clock}
Solutions from ICS. The ICS8524 has two select-
able clock inputs. The CLK, nCLK pair can accept
most standard differential input levels. The PCLK, nPCLK pair
can accept LVPECL, CML, or SSTL input levels. The device is
internally synchronized to eliminate runt pulses on the outputs
during asynchronous assertion/deassertion of the OE pin. The
ICS8524’s low output and part-to-part skew characteristics
make it ideal for workstation, server, and other high performance
clock distribution applications.
FEATURES
• 22 differential HSTL outputs
each with the ability to drive 50Ω to ground
• Selectable differential CLK, nCLK or LVPECL clock inputs
• CLK, nCLK pair can accept the following differential
input levels: LVPECL, LVDS, HSTL, SSTL, HCSL
• PCLK, nPCLK supports the following input types:
LVPECL, CML, SSTL
• Maximum output frequency: 500MHz
• Translates any single-ended input signal (LVCMOS, LVTTL,
GTL) to HSTL levels with resistor bias on nCLK input
• Output skew: 80ps (maximum)
• Part-to-part skew: 700ps (maximum)
• Jitter, RMS: 0.04ps (typical)
• LVPECL and HSTL mode operating voltage supply range: V_DD
= 3.3V ± 5%, V_DDO = 1.6V to 2V, GND = 0V
• 0°C to 85°C ambient operating temperature
• Pin compatible with the SY89824L and NB100EP223
BLOCK DIAGRAM
PIN ASSIGNMENT
CLK_SEL
CLK
nCLK
0
PCLK
nPCLK
1
OE
LE
Q
D
22 _Q0:Q21
22 _nQ0:nQ21
VDDO
nQ6
Q6
nQ5
Q5
nQ4
Q4
nQ3
Q3
nQ2
Q2
nQ1
Q1
nQ0
Q0
VDDO
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
49
32
50
31
51
30
52
29
53
28
54
27
55
26
56
ICS8524
25
57
24
58
23
59
22
60
21
61
20
62
19
63
18
64
17
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
VDDO
Q14
nQ14
Q15
nQ15
Q16
nQ16
Q17
nQ17
Q18
nQ18
Q19
nQ19
Q20
nQ20
VDDO
8524AY
64-Lead TQFP E-Pad
10mm x 10mm x 1.0mm package body
Y package
Top View
www.icst.com/products/hiperclocks.html
1
REV. B AUGUST 1, 2007