F1451 Datasheet, PDF (1/28 Pages) Integrated Device Technology – TX Digital VGA 700 MHz to 1100 MHz

T
TX Digital VGA
700 MHz to 1100 MHz
F1451
Datasheet
Description
The F1451 is a High Gain / High Linearity 700 MHz to 1100 MHz
TX Digital Variable Gain Amplifier used in transmitter applications.
The F1451 TX DVGA provides 32 dB maximum gain with
+41.5 dBm OIP3 and 3.6 dB noise figure. Up to 29.5 dB gain
control is achieved using the combination of a digital step
attenuator (DSA) and a KLINTM RF Digital Gain Amplifier. This
device uses a single 5 V supply and 185 mA of ICC.
This device is packaged in a 6 mm x 6 mm, 28-pin QFN with 50 Ω
single-ended RF input and RF output impedances for ease of
integration into the signal-path.
Competitive Advantage
In typical Base Stations, RF VGAs are used in the TX traffic paths
to drive the transmit power amplifier. The F1451 TX DVGA offers
very high reliability due to its construction from a monolithic silicon
die in a QFN package. The F1451 is configured to provide an
optimum balance of noise and linearity performance consisting of
a KLINTM RF amplifier, digital step attenuator (DSA) and a PA driver
amplifier. The KLINTM amplifier maintains the OIP3 and output P1dB
performance over an extended attenuation range when compared
to competitive devices.
Typical Applications
 Multi-mode, Multi-carrier Transmitters
 WiMAX and LTE Base Stations
 UMTS/WCDMA 3G Base Stations
 PHS/PAS Base Stations
 Public Safety Infrastructure
Features
 Broadband 700 MHz to 1100 MHz
 32 dB max gain
 3.6 dB NF @ max gain (900 MHz)
 29.5 dB total gain control range, 0.5 dB step
 < 2 dB overshoot between gain transitions
 Maintains flat +23 dBm OP1dB for more than 13 dB gain
adjustment range
 Maintains flat +41 dBm OIP3 for more than 15 dB gain
adjustment range
 SPI interface for DSA control
 Single 5 V supply voltage
 ICC = 185 mA
 Up to +105 °C TCASE operating temperature
 50 Ω input and output impedance
 Standby mode for power savings
 Pin compatible 2100 MHz and 2700 MHz versions
 6 mm x 6 mm, 28-pin QFN package
Block Diagram
Figure 1. Block Diagram
RF IN
KLIN
Constant
High Linearity^TM
K_LIN^TM DVGA
DSA
PA Driver
RF OUT
SPI &
Decoder
6 mm x 6 mm
28-pin
3
Digital CTL
Bias
/STBY
© 2016 Integrated Device Technology, Inc.
1
November 29, 2016