CPS-1848_17 Datasheet, PDF (1/86 Pages) Integrated Device Technology – 18-Port, 48-Lane, 240Gbps, Gen2 RapidIO Switch

18-Port, 48-Lane, 240Gbps,
Gen2 RapidIO Switch
CPS-1848
Datasheet
Description
The CPS-1848 (80HCPS1848) is a RapidIO Specification (Rev. 2.1)
compliant Central Packet Switch whose functionality is central to
routing packets for distribution among DSPs, processors, FPGAs,
other switches, or any other RapidIO-based devices. It can also be
used in RapidIO backplane switching. The CPS-1848 supports Serial
RapidIO (S-RIO) packet switching (unicast, multicast, and an optional
broadcast) from any of its 18 input ports to any of its 18 output ports.
Block Diagram
Quadrant 0
Lanes 0-3, 16-19, 32-35
Ports 0, 4, 8, 12, 16
Quadrant 3
Lanes 12-15, 28-31, 44-47
Ports 3, 7, 11, 15
CPS-1848
RapidIO Gen2
Switch Fabric
Event Management and Maintenance
Registers
I²C Controller
JTAG Controller
Ports 1, 5, 9, 13, 17
Lanes 4-7, 20-23, 36-39
Quadrant 1
Ports 2, 6, 10, 14
Lanes 8-11, 24-27, 40-43
Quadrant 2
Typical Applications
• High-performance computing
• Wireless
• Defense and aerospace
• Video and imaging
Features
• RapidIO ports
— 48 bidirectional S-RIO lanes
— Port widths of 1x, 2x, and 4x allow up to 20 Gbps per port
— Port speeds selectable: 6.25, 5, 3.125, 2.5, or 1.25 Gbaud
— Support Level I defined short or long haul reach, and Level II
defined short-, medium-, or long-run reach for each PHY speed
— Error Management Extensions support
— Software-assisted error recovery, supporting hot swap
• I²C Interfaces
— Provides I²C port for maintenance and error reporting
— Master or Slave operation
— Master allows power-on configuration from external ROM
— Master mode configuration with external image compressing and
checksum
• Switch
— 240 Gbps peak throughput
— Non-blocking data flow architecture
— Configurable for Cut-Through or Store-and-Forward data flow
— Very low latency for all packet lengths and load conditions
— Internal queuing buffer and retransmit buffer
— Standard transmitter- or receiver-controlled flow control
— Global routing or Local Port routing capability
— Supports up to 40 simultaneous multicast masks, with broadcast
— Performance monitoring counters for performance and
diagnostics analysis. Per input port and output port counters
• SerDes
— Transmitter pre-emphasis and drive strength + receiver
equalization provides best possible signal integrity
— Embedded PRBS generation and detection with programmable
polynomials support Bit Error Rate testing
• Additional Information
— Packet Trace/Mirror. Each input port can copy all incoming
packets matching user-defined criteria to a “trace” output port.
— Packet Filter. Each input port can filter (drop) all incoming packets
matching user-defined criteria.
— Device configurable through any of S-RIO ports, I²C, or JTAG
— Full JTAG Boundary Scan Support (IEEE1149.1 and 1149.6)
— Lidded/Lidless 784-FCBGA Package: 29  29 mm, 1.0 mm ball
pitch
©2017 Integrated Device Technology, Inc.
1
June 26, 2017