CPS-1848 Datasheet, PDF (1/1 Pages) Integrated Device Technology – IDT Serial RapidIO Switch Feature ComparisonChart

Integrated DeviceTechnology
IDT Serial RapidIO^® Switch Feature ComparisonChart
FEATURES
Performance and Configurability
Serial RapidIO specifications
Aggregate peak throughput (Gbps)
Full mesh non-blocking fabric
Asymmetric non-blocking fabric
Maximum of number of x4 ports
Maximum of number of x2 ports
Maximum of number of x1 port
Cut-through latency (ns)
Store and forward mode
Configurable by speed
SerDes and Power
Power per 10 Gbps link (typical, mW)
Identical long and short reach power
Per port power down
Programmable transmit drive strength and pre-emphasis
Programmable receive equalization
On-die scope capability
Multicast and Routing
Per port multicast architecture
Parallel multicast engine with QoS support
Per port multicast masks/groups
8- and 16-bit addressing
Programmable watermarks on ingress buffers
RapidIO Standard and Non-Standard Features
Packet/trace/mirror/ filter for debug
Traffic management through user selectable
scheduling algorithms
Receiver controlled flow control
Transmitter controlled flow control
Performance counters/monitors
Dedicated maintenance path for “5th priority”
Error Management features exceeding S-RIO specification
Error log (history) and broad error detection coverage
Link-layer AES-128 encryption
BOM Reduction and Clocking Options
Clocking options (MHz)
No power-up sequence or ramp rate requirements
Run RapidIO at CPRI and OBSAI speeds
Lane swap for board design simplification
Debug packet generator
Debug packet capture
Other Bridging and Unique features
Built-in hardware bridging from RapidIO to PCI
Built-in bridging options to non-SerDes FPGA
Package (mm)
CPS-1848
2.1
240
√
12
18
18
100
√
Each Quad
<300
√
√
√
√
40
√
√
√
√
√
√
√
√
√
√
156
√
√
29 X 29
IDT | THE ANALOG + DIGITAL COMPANY
CPS-1432
CPS/SPS-1616
CPS-6Q
/10Q CPS-8 / 12
/ 16 Tsi572 / 574
/ 578
Tsi577
Tsi620
2.1
160
√
8
14
14
100
√
Each Quad
2.1
80
√
4
8
16
100
√
CPS/SPS - Each Lane
1.3
1.3
1.3
1.3
1.3
60
100
20
30
40
√
√
√
√
√
6
10
2
3
4
16
190
√
Each Quad
16
190
√
Each Quad
8
12
16
190
190
190
√
√
√
Each Lane Pair
1.3
1.3
1.3
30
40
80
√
√
√
2
4
8
8
8
16
110
110
110
√
√
√
Each MAC
1.3
1.3
40
50
√
√
4
3
16
110
√
Each Quad
6
110
√
Each MAC
<385
CPS/SPS <440
√
√
√
√
√
√
<500
√
√
√
√
<500
<500
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
<500
<500
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
40
40
40
40
10
10
10
8
8
8
8
8
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
SPS on 4 1x Ports
156
156
√
√
√
√
156
√
√
156
√
√
√
156 or 125
156 or 125 156 or 125
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
25 x 25
21 X 21
27 X 27
√
√
27 X 27
19 X 19
19 X 19
19 X 19 21 X 21 21 X 21 27 X 27
21 X 21
27 X 27
GD_S-RIO Switches_REVB0311
IDT Serial RapidIO Switch Feature Comparison