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CPS-1616 Datasheet, PDF (1/77 Pages) Integrated Device Technology – 16-Port, 16-Lane, 80Gbps, Gen2 RapidIO Switch | |||
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16-Port, 16-Lane, 80Gbps,
Gen2 RapidIO Switch
CPS-1616
Datasheet
Description
The CPS-1616 (80HCPS1616) is a RapidIO Specification (Rev. 2.1)
compliant Central Packet Switch whose functionality is central to
routing packets for distribution among DSPs, processors, FPGAs,
other switches, or any other RapidIO-based devices. It can also be
used in RapidIO backplane switching. The CPS-1616 supports Serial
RapidIO (S-RIO) packet switching (unicast, multicast, and an optional
broadcast) from any of its 16input ports to any of its 16 output ports.
Block Diagram
Quadrant 0
Lanes 0-3
Ports 0-3
Quadrant 3
Lanes 12-15
Ports 12-15
CPS-1616
RapidIO Gen2
Switch Fabric
Event Management and Maintenance
Registers
I2C Controller
JTAG Controller
Ports 4-7
Ports 8-11
Lanes 4-7
Quadrant 1
Lanes 8-11
Quadrant 2
Typical Applications
⢠High-performance computing
⢠Wireless
⢠Defense and aerospace
⢠Video and imaging
Features
⢠RapidIO ports
â 16 bidirectional S-RIO lanes
â Port widths of 1x, 2x, and 4x allow up to 20 Gbps per port
â Port speeds selectable: 6.25, 5, 3.125, 2.5, or 1.25 Gbaud
â Support Level I defined short or long haul reach, and Level II
defined short-, medium-, or long-run reach for each PHY speed
â Error Management Extensions support
â Software-assisted error recovery, supporting hot swap
⢠I2C Interfaces
â Provides I2C port for maintenance and error reporting
â Master or Slave operation
â Master allows power-on configuration from external ROM
â Master mode configuration with external image compressing and
checksum
⢠Switch
â 80 Gbps peak throughput
â Non-blocking data flow architecture
â Configurable for Cut-Through or Store-and-Forward data flow
â Very low latency for all packet lengths and load conditions
â Internal queuing buffer and retransmit buffer
â Standard transmitter- or receiver-controlled flow control
â Global routing or Local Port routing capability
â Supports up to 40 simultaneous multicast masks, with broadcast
â Performance monitoring counters for performance and
diagnostics analysis. Per input port and output port counters
⢠SerDes
â Transmitter pre-emphasis and drive strength + receiver
equalization provides best possible signal integrity
â Embedded PRBS generation and detection with programmable
polynomials support Bit Error Rate testing
⢠Additional Information
â Packet Trace/Mirror. Each input port can copy all incoming
packets matching user-defined criteria to a âtraceâ output port.
â Packet Filter. Each input port can filter (drop) all incoming packets
matching user-defined criteria.
â Device configurable through any of S-RIO ports, I2C, or JTAG
â Full JTAG Boundary Scan Support (IEEE1149.1 and 1149.6)
â Lidded/Lidless 784-FCBGA Package: 21 ï´ï 21 mm, 1.0 mm ball
pitch
©2017 Integrated Device Technology, Inc.
1
June 26, 2017
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