9FGV0831_16 Datasheet, PDF (1/17 Pages) Integrated Device Technology – 8-O/P 1.8V PCIe Gen 1/2/3 Clock Generator

8-O/P 1.8V PCIe Gen 1/2/3 Clock Generator
9FGV0831
DATASHEET
Description
The 9FGV0831 is a member of IDT's SOC-Friendly 1.8V
Very-Low-Power PCIe clock family. The device has 8 output
enables for clock management, 2 different spread spectrum
levels in addition to spread off and 2 selectable SMBus
addresses.
Recommended Application
1.8V PCIe Gen1/2/3 clock generator
Output Features
• 8 - 100MHz Low-Power (LP) HCSL DIF pair
• 1 - 1.8V LVCMOS REF output w/Wake-On-LAN (WOL)
support
Key Specifications
• DIF cycle-to-cycle jitter <50ps
• DIF output-to-output skew <50ps
• DIF phase jitter is PCIe Gen1-2-3 compliant
• REF phase jitter is < 1.5ps RMS
Block Diagram
Features/Benefits
• LP-HCSL outputs; save 16 resistors compared to standard
PCIe devices
• 62mW typical power consumption; reduced thermal
concerns
• Outputs can optionally be supplied from any voltage
between 1.05 and 1.8V; maximum power savings
• OE# pins; support DIF power management
• Programmable Slew rate for each output; allows tuning for
various line lengths
• Programmable output amplitude; allows tuning for various
application environments
• DIF outputs blocked until PLL is locked; clean system
start-up
• Selectable 0%, -0.25% or -0.5% spread on DIF outputs;
reduces EMI
• External 25MHz crystal; supports tight ppm with 0 ppm
synthesis error
• Configuration can be accomplished with strapping pins;
SMBus interface not required for device control
• 3.3V tolerant SMBus interface works with legacy controllers
• Selectable SMBus addresses; multiple devices can easily
share an SMBus segment
• Space saving 48-pin 6x6 mm VFQFPN; minimal board
space
vOE(7:0)#
XIN/CLKIN_25
X2
OSC
vSADR
vSS_EN_tri
^CKPWRGD_PD#
SDATA_3.3
SCLK_3.3
CONTROL
LOGIC
SS Capable PLL
REF1.8
DIF7
DIF6
DIF5
DIF4
DIF3
DIF2
DIF1
DIF0
9FGV0831 OCTOBER 18, 2016
1
©2016 Integrated Device Technology, Inc.