9FGV0431_17 Datasheet, PDF (1/16 Pages) Integrated Device Technology – 4-OUTPUT VERY LOW POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR

4-OUTPUT VERY LOW POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR
DATASHEET
9FGV0431
Description
The 9FGV0431 is a 4-output very low-power clock
generator for PCIe Gen 1, 2, 3 and 4 applications. The
device has 4 output enables for clock management and
supports 2 different spread spectrum levels in addition to
spread off.
Recommended Application
PCIe Gen1-4 clock generation for Riser Cards, Storage,
Networking, JBOD, Communications, Access Points
Output Features
• 4 – 0.7V low-power HCSL-compatible (LP-HCSL) DIF
pairs
• 1 – 1.8V LVCMOS REF output w/Wake-On-Lan
Key Specifications
• DIF cycle-to-cycle jitter <50ps
• DIF output-to-output skew <50ps
• DIF phase jitter is PCIe Gen1-2-3-4 compliant
• REF phase jitter is < 1.5ps RMS
Block Diagram
Features/Benefits
• 1.8V operation; reduced power consumption
• OE# pins; support DIF power management
• LP-HCSL differential clock outputs; reduced power and
board space
• Programmable Slew rate for each output; allows tuning
for various line lengths
• Programmable output amplitude; allows tuning for
various application environments
• DIF outputs blocked until PLL is locked; clean system
start-up
• Selectable 0%, -0.25% or -0.5% spread on DIF outputs;
reduces EMI
• External 25MHz crystal; supports tight ppm with 0 ppm
synthesis error
• Configuration can be accomplished with strapping pins;
SMBus interface not required for device control
• 3.3V tolerant SMBus interface works with legacy
controllers
• Space saving 32-pin 5x5 mm MLF; minimal board space
• Selectable SMBus addresses; multiple devices can
easily share an SMBus segment
X1_25
X2
OE(3:0)#
OSC
SS Capable PLL
REF1.8
4
DIF(3:0)
SADR
SS_EN_tri
CKPWRGD_PD#
SDATA_3.3
SCLK_3.3
CONTROL
LOGIC
IDT® 4-OUTPUT VERY LOW POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR
1
9FGV0431
JUNE 22, 2017