9FGU0641_16 Datasheet, PDF (1/15 Pages) Integrated Device Technology – 6 O/P 1.5V PCIe Gen1-2-3 Clock Generator

6 O/P 1.5V PCIe Gen1-2-3 Clock Generator
w/Zo=100ohms
9FGU0641
DATASHEET
Description
The 9FGU0641 is a member of IDT's 1.5V Ultra-Low-Power
PCIe clock family with integrated output terminations
providing Zo=100ohms. The device has 6 output enables for
clock management and supports 2 different spread spectrum
levels in addition to spread off.
Recommended Application
1.5V PCIe Gen1-2-3 clock generator
Output Features
• 6 -100MHz Low-power HCSL (LP-HCSL) DIF pairs
w/Zo=100
• 1 - 1.5V LVCMOS REF output w/Wake-On-LAN (WOL)
support
Key Specifications
• DIF cycle-to-cycle jitter <50ps
• DIF output-to-output skew <60ps
• DIF phase jitter is PCIe Gen1-2-3 compliant
• REF phase jitter is < 3.0ps RMS
Block Diagram
Features/Benefits
• Direct connection to 100ohm transmission lines; saves 24
resistors compared to standard PCIe device
• 45mW typical power consumption; reduced thermal
concerns
• Outputs can optionally be supplied from any voltage
between 1.05 and 1.5V; maximum power savings
• OE# pins; support DIF power management
• Programmable Slew rate for each output; allows tuning for
various line lengths
• Programmable output amplitude; allows tuning for various
application environments
• DIF outputs blocked until PLL is locked; clean system
start-up
• Selectable 0%, -0.25% or -0.5% spread on DIF outputs;
reduces EMI
• External 25MHz crystal; supports tight ppm with 0 ppm
synthesis error
• Configuration can be accomplished with strapping pins;
SMBus interface not required for device control
• Selectable SMBus addresses; multiple devices can easily
share an SMBus segment
• 3.3V tolerant SMBus interface works with legacy controllers
• Space saving 40-pin 5x5 mm VFQFPN; minimal board
space
X1_25
X2
vOE(5:0)#
OSC
REF1.8
6
DIF5
vSADR
vSS_EN_tri
^CKPWRGD_PD#
SDATA_3.3
SCLK_3.3
CONTROL
LOGIC
SS Capable PLL
DIF4
DIF3
DIF2
DIF1
DIF0
9FGU0641 OCTOBER 18, 2016
1
©2016 Integrated Device Technology, Inc.