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9FGU0231_16 Datasheet, PDF (1/15 Pages) Integrated Device Technology – 2 O/P 1.5V PCIe Gen1-2-3 Clock Generator | |||
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2 O/P 1.5V PCIe Gen1-2-3 Clock Generator
9FGU0231
DATASHEET
Description
The 9FGU0231 is a member of IDT's 1.5V Ultra-Low-Power
PCIe clock family. The device has 2output enables for clock
management, 2 different spread spectrum levels in addition to
spread off and 2 selectable SMBus addresses.
Recommended Application
1.5V PCIe Gen1-2-3 clock generator
Output Features
⢠2 - 100MHz Low-Power (LP) HCSL DIF pairs
⢠1 - 1.5V LVCMOS REF output w/Wake-On-LAN (WOL)
support
Key Specifications
⢠DIF cycle-to-cycle jitter <50ps
⢠DIF output-to-output skew <50ps
⢠DIF phase jitter is PCIe Gen1-2-3 compliant
⢠REF phase jitter is < 3.0ps RMS
Features/Benefits
⢠LP-HCSL outputs; save 4 resistors compared to standard
PCIe devices
⢠23mW typical power consumption; reduced thermal
concerns
⢠OE# pins; support DIF power management
⢠Programmable Slew rate for each output; allows tuning for
various line lengths
⢠Programmable output amplitude; allows tuning for various
application environments
⢠DIF outputs blocked until PLL is locked; clean system
start-up
⢠Selectable 0%, -0.25% or -0.5% spread on DIF outputs;
reduces EMI
⢠External 25MHz crystal; supports tight ppm with 0 ppm
synthesis error
⢠Configuration can be accomplished with strapping pins;
SMBus interface not required for device control
⢠Selectable SMBus addresses; multiple devices can easily
share an SMBus segment
⢠3.3V tolerant SMBus interface works with legacy controllers
⢠Space saving 24-pin 4x4 mm VFQFPN; minimal board
space
Block Diagram
XIN/CLKIN_25
X2
vOE(1:0)#
OSC
vSADR
vSS_EN_tri
^CKPWRGD_PD#
SDATA_3.3
SCLK_3.3
CONTROL
LOGIC
SS Capable PLL
REF1.5
DIF1
DIF0
9FGU0231 OCTOBER 18, 2016
1
©2016 Integrated Device Technology, Inc.
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