9FGL04 Datasheet, PDF (1/18 Pages) Integrated Device Technology – control input polarity

4-output 3.3V PCIe Gen 1-2-3 Clock Generator
9FGL04
Description
The 9FGL0441/51/P1 are members of IDT's 3.3V Low-Power
(LP) PCIe family. The devices have 4 output enables for
clock management and support 2 different spread spectrum
levels in addition to spread off. The 9FGL0441/51/P1
supports both Common Clock (CC) with or without spread
spectrum and Separate Reference no-Spread (SRnS) PCIe
clocking architectures. The 9FGL04P1 can be programmed
with a user-defined power up default SMBus configuration.
Recommended Application
3.3V PCIe Gen1-2-3 Clock Generator
Output Features
• 4 – 100 MHz Low-Power HCSL (LP-HCSL) DIF pairs
• 9FGL0441 default ZOUT = 100
• 9FGL0451 default ZOUT = 85
• 9FGL04P1 factory programmable defaults
• 1 - 3.3V LVCMOS REF output w/Wake-On-LAN (WOL)
support
Key Specifications
• DIF cycle-to-cycle jitter <50ps
• DIF output-to-output skew <50ps
• DIF phase jitter is PCIe Gen1-2-3 compliant with SSC on or
off
• DIF 12k-20M phase jitter is <3ps rms when SSC is off
• REF phase jitter is <300fs rms (SSC off) and < 1ps RMS
(SSC on)
• ±100ppm frequency accuracy on all clocks
Block Diagram
XIN/CLKIN_25
X2
vOE(3:0)#
OSC
DATASHEET
Features/Benefits
• Direct connection to 100 (xx41) or 85 (xx51)
transmission lines; saves 16 resistors compared to
standard PCIe devices
• 142mW typical power consumption; eliminates thermal
concerns
• SMBus-selectable features allows optimization to customer
requirements:
• control input polarity
• control input pull up/downs
• slew rate for each output
• 33, 85 or 100Ω output impedance for each output
• spread spectrum amount
• 41 and 51 devices contain default configuration; SMBus
interface not required for device operation
• P1 device allows factory programming of customer-defined
SMBus power up default; allows exact optimization to
customer requirements
• OE# pins; support DIF power management
• 8MHz – 40MHz input frequency (25MHz default); flexibility
• Pin/SMBus selectable 0%, -0.25% or -0.5% spread on DIF
outputs %; minimize EMI and phase jitter for each
application
• DIF outputs blocked until PLL is locked; clean system
start-up
• Two selectable SMBus addresses; multiple devices can
easily share an SMBus segment
• Space saving 32-pin 5x5mm VFQFPN; minimal board
space
REF3.3
vSADR
vSS_EN_tri
^CKPWRGD_PD#
SDATA_3.3
SCLK_3.3
CONTROL
LOGIC
SS Capable PLL
DIF3
DIF2
DIF1
DIF0
Note: Resistors default to internal on 41/51 devices. P1 devices have programmable default impedances on an output-by-output basis.
9FGL04 REVISION B 08/06/15
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©2015 Integrated Device Technology, Inc.