|
9DBV0931 Datasheet, PDF (1/17 Pages) Integrated Circuit Systems – Programmable Slew rate for each output | |||
|
9 O/P 1.8V PCIe Gen1-2-3 Fan-out Buffer
9DBV0931
DATASHEET
Description
The 9DBV0931 is a member of IDT's 1.8V Very-Low-Power
(VLP) PCIe family. The device has 9 output enables for clock
management, and 3 selectable SMBus addresses.
Recommended Application
1.8V PCIe Gen1-2-3 Fan-out Buffer (FOB)
Output Features
⢠9 - 1-200MHz Low-Power (LP) HCSL DIF pairs
Key Specifications
⢠DIF additive cycle-to-cycle jitter <5ps
⢠DIF output-to-output skew < 60ps
⢠DIF additive phase jitter is <100fs rms for PCIe Gen3
⢠DIF additive phase jitter <300fs rms for SGMII
Block Diagram
Features/Benefits
⢠LP-HCSL outputs; save 18 resistors compared to standard
HCSL outputs
⢠53mW typical power consumption; minimal power
consumption
⢠OE# pins; support DIF power management
⢠HCSL compatible differential input; can be driven by
common clock sources
⢠Programmable Slew rate for each output; allows tuning for
various line lengths
⢠Programmable output amplitude; allows tuning for various
application environments
⢠1MHz to 200MHz operating frequency
⢠3.3V tolerant SMBus interface works with legacy controllers
⢠Selectable SMBus addresses; multiple devices can easily
share an SMBus segment
⢠Device contains default configuration; SMBus interface not
required for device operation
⢠Space saving 48-pin 6x6mm VFQFPN; minimal board
space
vOE(8:0)#
9
CLK_IN
CLK_IN#
vSADR
^CKPWRGD_PD#
SDATA_3.3
SCLK_3.3
CONTROL
LOGIC
DIF8
DIF7
DIF6
DIF5
DIF4
DIF3
DIF2
DIF1
DIF0
9DBV0931 REVISION C 08/28/14
1
©2014 Integrated Device Technology, Inc.
|
▷ |