9DBV0631 Datasheet, PDF (1/17 Pages) Integrated Circuit Systems – 55mW typical power consumption in PLL mode

6 O/P 1.8V PCIe Gen1-2-3 ZDB/FOB
9DBV0631
DATASHEET
Description
The 9DBV0631 is a member of IDT's 1.8V Very-Low-Power
(VLP) PCIe family. The device has 6 output enables for clock
management and 3 selectable SMBus addresses.
Recommended Application
1.8V PCIe Gen1-2-3 Zero Delay/Fanout Buffer (ZDB/FOB)
Output Features
• 6 - 1-200 MHz Low-Power (LP) HCSL DIF pairs
Key Specifications
• DIF additive cycle-to-cycle jitter <5ps
• DIF output-to-output skew <60ps
• DIF additive phase jitter is <100fs rms for PCIe Gen3
• DIF additive phase jitter <300fs rms for SGMII
Block Diagram
Features/Benefits
• LP-HCSL outputs; save 12 resistors compared to standard
PCIe devices
• 55mW typical power consumption in PLL mode; minimal
power consumption
• Outputs can optionally be supplied from any voltage
between 1.05 and 1.8V; maximum power savings
• OE# pins; support DIF power management
• HCSL-compatible differential input; can be driven by
common clock sources
• Spread Spectrum tolerant; allows reduction of EMI
• Programmable Slew rate for each output; allows tuning for
various line lengths
• Programmable output amplitude; allows tuning for various
application environments
• Pin/software selectable PLL bandwidth and PLL Bypass;
minimize phase jitter for each application
• Outputs blocked until PLL is locked; clean system start-up
• Configuration can be accomplished with strapping pins;
SMBus interface not required for device control
• 3.3V tolerant SMBus interface works with legacy
controllers
• Space saving 40-pin 5x5mm MLF; minimal board space
• 3 selectable SMBus addresses; multiple devices can easily
share an SMBus segment
vOE(5:0)#
6
CLK_IN
CLK_IN#
vSADR
^vHIBW_BYPM_LOBW#
^CKPWRGD_PD#
SDATA_3.3
SCLK_3.3
SS-
Compatible
PLL
CONTROL
LOGIC
DIF5
DIF4
DIF3
DIF2
DIF1
DIF0
9DBV0631 REVISION E 09/11/14
1
©2014 Integrated Device Technology, Inc.