9DBU0941 Datasheet, PDF (1/17 Pages) Integrated Circuit Systems – slew rate for each output

9 O/P 1.5V PCIe Gen1-2-3 Fan-out Buffer
w/Zo=100ohms
9DBU0941
DATASHEET
Description
The 9DBU0941 is a member of IDT's 1.5V Ultra-Low-Power
(ULP) PCIe family. It has integrated terminations for direct
connection to 100ohm transmission lines. The device has 9
output enables for clock management, and 3 selectable
SMBus addresses.
Recommended Application
1.5V PCIe Gen1-2-3 Fanout Buffer (FOB)
Output Features
• 9 – 1-167MHz Low-Power (LP) HCSL DIF pairs
w/ZO=100
Key Specifications
• DIF additive cycle-to-cycle jitter <5ps
• DIF output-to-output skew < 60ps
• DIF additive phase jitter is <300fs rms for PCIe Gen3
• DIF additive phase jitter <350s rms for SGMII
Block Diagram
Features/Benefits
• Direct connection to 100ohm transmission lines; save 36
resistors compared to standard HCSL outputs
• 47mW typical power consumption; eliminates thermal
concerns
• Outputs can optionally be supplied from any voltage
between 1.05 and 1.5V; maximum power savings
• Spread Spectrum (SS) compatible; allows SS for EMI
reduction
• OE# pins for each output; support DIF power management
• HCSL-compatible differential input; can be driven by
common clock sources
• SMBus-selectable features; optimize signal integrity to
application
• slew rate for each output
• differential output amplitude
• Device contains default configuration; SMBus interface not
required for device operation
• Selectable SMBus addresses; multiple devices can easily
share an SMBus segment
• 3.3V tolerant SMBus interface works with legacy controllers
• Space saving 48-pin 6x6mm VFQFPN; minimal board
space
,
vOE(8:0)#
9
CLK_IN
CLK_IN#
vSADR
^CKPWRGD_PD#
SDATA_3.3
SCLK_3.3
CONTROL
LOGIC
DIF8
DIF7
DIF6
DIF5
DIF4
DIF3
DIF2
DIF1
DIF0
9DBU0941 REVISION C 04/22/15
1
©2015 Integrated Device Technology, Inc.