9DBU0741 Datasheet, PDF (1/17 Pages) Integrated Circuit Systems – slew rate for each output

7-Output 1.5V PCIe Gen1-2-3 Fanout Buffer
with Zo=100ohms
9DBU0741
DATASHEET
Description
The 9DBU0741 is a member of IDT's 1.5V Ultra-Low-Power
(ULP) PCIe family. It has integrated terminations for direct
connection to 100 transmission lines. The device has 7
output enables for clock management, and 3 selectable
SMBus addresses.
Recommended Application
1.5V PCIe Gen1-2-3 Fanout Buffer (FOB)
Output Features
• 7 – 1–167MHz Low-Power (LP) HCSL DIF pairs with
Zo=100
Key Specifications
• DIF additive cycle-to-cycle jitter < 5ps
• DIF output-to-output skew < 60ps
• DIF additive phase jitter is < 300fs rms for PCIe Gen3
• DIF additive phase jitter < 350s rms for SGMII
Block Diagram
vOE(6:0)#
7
CLK_IN
CLK_IN#
vSADR
^CKPWRGD_PD#
SDATA_3.3
SCLK_3.3
CONTROL
LOGIC
Features/Benefits
• Integrated terminations; save 28 resistors compared to
standard HCSL outputs
• 36mW typical power consumption; eliminates thermal
concerns
• Outputs can optionally be supplied from any voltage
between 1.05V and 1.5V; maximum power savings
• Spread Spectrum (SS) compatible; allows SS for EMI
reduction
• OE# pins for each output; support DIF power management
• HCSL-compatible differential input; can be driven by
common clock sources
• SMBus-selectable features; optimize signal integrity to
application
• slew rate for each output
• differential output amplitude
• Device contains default configuration; SMBus interface not
required for device operation
• Selectable SMBus addresses; multiple devices can easily
share an SMBus segment
• 3.3V tolerant SMBus interface works with legacy controllers
• 5 × 5 mm 40-VFQFPN package; minimal board space
DIF6
DIF5
DIF4
DIF3
DIF2
DIF1
DIF0
9DBU0741 MARCH 8, 2017
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©2017 Integrated Device Technology, Inc.