9DBU0541 Datasheet, PDF (1/16 Pages) Integrated Circuit Systems – slew rate for each output

5 O/P 1.5V PCIe Gen1-2-3 Fan-out Buffer
w/Zo=100ohms
9DBU0541
DATASHEET
Description
The 9DBU0541 is a member of IDT's 1.5V Ultra-Low-Power
(ULP) PCIe family. It has integrated terminations for direct
connection to 100 transmission lines. The device has 5
output enables for clock management, and 3 selectable
SMBus addresses.
Recommended Application
1.5V PCIe Gen1-2-3 Fan-out Buffer (FOB)
Output Features
• 5 - 1-167MHz Low-Power (LP) HCSL DIF pairs
w/ZO=100
Key Specifications
• DIF additive cycle-to-cycle jitter <5ps
• DIF output-to-output skew <60ps
• DIF additive phase jitter is <300fs rms for PCIe Gen3
• DIF additive phase jitter <350s rms for SGMII
Features/Benefits
• Integrated terminations; save 20 resistors compared to
standard HCSL outputs
• 35mW typical power consumption; eliminates thermal
concerns
• Spread Spectrum (SS) compatible; allows SS for EMI
reduction
• OE# pins; support DIF power management
• HCSL-compatible differential input; can be driven by
common clock sources
• SMBus-selectable features; optimize signal integrity to
application
• slew rate for each output
• differential output amplitude
• Device contains default configuration; SMBus interface not
required for device contro
• 3.3V tolerant SMBus interface works with legacy controllers
• Selectable SMBus addresses; multiple devices can easily
share an SMBus segment
• Space saving 32-pin 5x5mm VFQFPN; minimal board
space
Block Diagram
vOE(4:0)#
CLK_IN
CLK_IN#
vSADR
^CKPWRGD_PD#
SDATA_3.3
SCLK_3.3
5
CONTROL
LOGIC
DIF4
DIF3
DIF2
DIF1
DIF0
9DBU0541 REVISION D 04/22/15
1
©2015 Integrated Device Technology, Inc.