8T74S208 Datasheet, PDF (1/18 Pages) Integrated Device Technology – One differential input reference clock

2.5V Differential LVDS Clock Divider
and Fanout Buffer
8T74S208
DATA SHEET
General Description
The 8T74S208 is a high-performance differential LVDS clock divider
and fanout buffer. The device is designed for the frequency division
and signal fanout of high-frequency, low phase-noise clocks. The
8T74S208 is characterized to operate from a 2.5V power supply.
Guaranteed output-to-output and part-to-part skew characteristics
make the 8T74S208 ideal for those clock distribution applications
demanding well-defined performance and repeatability. The
integrated input termination resistors make interfacing to the
reference source easy and reduce passive component count. Each
output can be individually enabled or disabled in the high-impedance
state controlled by a I²C register. On power-up, all outputs are
enabled.
Features
• One differential input reference clock
• Differential pair can accept the following differential input
levels: LVDS, LVPECL, CML
• Integrated input termination resistors
• Eight LVDS outputs
• Selectable clock frequency division of ÷1, ÷2, ÷4 and ÷8
• Maximum input clock frequency: 1GHz
• LVCMOS interface levels for the control inputs
• Individual output enabled/ disabled by I²C interface
• Output skew: 45ps (maximum)
• Output rise/fall times: 350ps (maximum)
• Low additive phase jitter, RMS: 96fs (typical)
• Full 2.5V supply voltage
• Outputs enabled at power up
• Lead-free (RoHS 6) 32-Lead VFQFN packaging
• -40°C to 85°C ambient operating temperature
Block Diagram
IN
nIN
50
f_REF
÷1, ÷2,
÷4, ÷8
50
V_T
FSEL[1:0] ^{Pulldown (2)}
2
SDA ^Pullup
SCL ^Pullup
I²C
8
ADR[1:0] ^{Pulldown (2)} ₂
Pin Assignment
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q4
nQ4
Q5
nQ5
Q6
nQ6
ADR1
GND
Q0
nQ0
Q1
nQ1
GND
V_DDO
32 31 30 29 28 27 26 25
1
24
2
23
3
22
4
21
8T74S208
5
20
6
19
7
18
8
17
9 10 11 12 13 14 15 16
FSEL0
GND
nQ7
Q7
nQ6
Q6
GND
V_DDO
Q7
32-Lead VFQFN
nQ7
5mm x 5mm x 0.925mm
package body
NL Package, Top View
8T74S208 REVISION 1 09/10/14
1
©2014 Integrated Device Technology, Inc.