8T73S208A-01_16 Datasheet, PDF (1/24 Pages) Integrated Device Technology – 2.5V, 3.3V Differential LVPECL Clock Divider and Buffer

2.5V, 3.3V Differential LVPECL Clock
Divider and Buffer
REFER TO PCN# N1605-01, Effective Date August 18, 2016
FOR NEW DESIGNS USE PART NUMBER: 8T73S208B-01NLGI
8T73S208A-01
DATA SHEET
General Description
The 8T73S208A-01 is a high-performance differential LVPECL clock
divider and fanout buffer. The device is designed for the frequency
division and signal fanout of high-frequency, low phase-noise clocks.
The 8T73S208A-01 is characterized to operate from a 2.5V and 3.3V
power supply. Guaranteed output-to-output and part-to-part skew
characteristics make the 8T73S208A-01 ideal for those clock
distribution applications demanding well-defined performance and
repeatability. The integrated input termination resistors make
interfacing to the reference source easy and reduce passive
component count. Each output can be individually enabled or
disabled in the high-impedance state controlled by a I²C register. On
power-up, all outputs are disabled.
Features
• One differential input reference clock
• Differential pair can accept the following differential input
levels: LVDS, LVPECL, CML
• Integrated input termination resistors
• Eight LVPECL outputs
• Selectable clock frequency division of ÷1, ÷2, ÷4 and ÷8
• Maximum input clock frequency: 1GHz
• LVCMOS interface levels for the control inputs
• Individual output enable/disabled by I²C interface
• Power-up state: all outputs disabled
• Output skew: 60ps (maximum)
• Output rise/fall times: 350ps (maximum)
• Low additive phase jitter, RMS: 182fs (typical)
• Full 2.5V and 3.3V supply voltages
• Lead-free (RoHS 6) 32-Lead VFQFN packaging
• -40°C to 85°C ambient operating temperature
8T73S208A-01 REVISION 2 05/20/16
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