8T73S208A-01 Datasheet, PDF (1/22 Pages) Integrated Device Technology – One differential input reference clock

2.5V, 3.3V Differential LVPECL Clock
Divider and Buffer
8T73S208A-01
DATA SHEET
General Description
The 8T73S208A-01 is a high-performance differential LVPECL clock
divider and fanout buffer. The device is designed for the frequency
division and signal fanout of high-frequency, low phase-noise clocks.
The 8T73S208A-01 is characterized to operate from a 2.5V and 3.3V
power supply. Guaranteed output-to-output and part-to-part skew
characteristics make the 8T73S208A-01 ideal for those clock
distribution applications demanding well-defined performance and
repeatability. The integrated input termination resistors make
interfacing to the reference source easy and reduce passive
component count. Each output can be individually enabled or
disabled in the high-impedance state controlled by a I²C register. On
power-up, all outputs are disabled.
Features
• One differential input reference clock
• Differential pair can accept the following differential input
levels: LVDS, LVPECL, CML
• Integrated input termination resistors
• Eight LVPECL outputs
• Selectable clock frequency division of ÷1, ÷2, ÷4 and ÷8
• Maximum input clock frequency: 1GHz
• LVCMOS interface levels for the control inputs
• Individual output enable/disabled by I²C interface
• Power-up state: all outputs disabled
• Output skew: 60ps (maximum)
• Output rise/fall times: 350ps (maximum)
• Low additive phase jitter, RMS: 182fs (typical)
• Full 2.5V and 3.3V supply voltages
• Lead-free (RoHS 6) 32-Lead VFQFN packaging
• -40°C to 85°C ambient operating temperature
Block Diagram
IN
nIN
50
f_REF
÷1, ÷2,
÷4, ÷8
50
V_T
FSEL[1:0]
Pulldown (2)
2
SDA
SCL
Pullup
Pullup
I²C
8
ADR[1:0]
Pulldown (2)
2
Pin Assignment
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q4
nQ4
Q5
nQ5
Q6
nQ6
ADR1
V_EE
Q0
nQ0
Q1
nQ1
V_EE
V_CCO
32 31 30 29 28 27 26 25
1
24
2
23
3
22
4
21
5
20
6
19
7
18
8
17
9 10 11 12 13 14 15 16
FSEL0
V_EE
nQ7
Q7
nQ6
Q6
V_EE
V_CCO
Q7
nQ7
32-pin, 5mm x 5mm VFQFN
8T73S208A-01 REVISION 1 06/15/15
1
©2015 Integrated Device Technology, Inc.