8SLVP1212I Datasheet, PDF (1/25 Pages) Integrated Device Technology – Low Phase Noise, 1-to-12, 3.3V, 2.5V LVPECL Output Fanout Buffer

Low Phase Noise, 1-to-12, 3.3V, 2.5V
LVPECL Output Fanout Buffer
IDT8SLVP1212I
DATASHEET
General Description
The IDT8SLVP1212I is a high-performance, 12 output differential
LVPECL fanout buffer. The device is designed for the fanout of
high-frequency, very low additive phase-noise clock and data signals.
The IDT8SLVP1212I is characterized to operate from a 3.3V and
2.5V power supply. Guaranteed output-to-output and part-to-part
skew characteristics make the IDT8SLVP1212I ideal for those clock
distribution applications demanding well-defined performance and
repeatability. Two selectable differential inputs and twelve low skew
outputs are available. The integrated bias voltage generators enables
easy interfacing of single-ended signals to the device inputs. The
device is optimized for low power consumption and low additive
phase noise.
Block Diagram
V_CC
PCLK0
nPCLK0
f_REF
V_CC
PCLK1
nPCLK1
SEL
V_REF
Voltage
Reference
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q4
nQ4
Q5
nQ5
Q6
nQ6
Q7
nQ7
Q8
nQ8
Q9
nQ9
Q10
nQ10
Q11
nQ11
Features
• Twelve low skew, low additive jitter LVPECL outputs
• Two selectable, differential clock inputs
• Differential pairs can accept the following differential input
levels: LVDS, LVPECL, CML
• Maximum input clock frequency: 2GHz
• LVCMOS interface levels for the control input (input select)
• Output skew: 33ps (maximum)
• Propagation delay: 550ps (maximum)
• Low additive phase jitter, RMS at f_REF = 156.25MHz, V_PP = 1V,
12kHz-20MHz: 60fs (maximum)
• Full 3.3V and 2.5V supply voltage
• Device current consumption (I_EE): 131mA (maximum)
• Available in Lead-free (RoHS 6), 40-Lead VFQFN package
• -40°C to 85°C ambient operating temperature
• Differential PCLK0, nPCLK0 and PCLK1, nPCLK1 pairs can also
accept single-ended LVCMOS levels. See Applications section
Wiring the Differential Input Levels to Accept Single-ended Levels
(Figure 1A and Figure 1B)
Pin Assignment
30 29 28 27 26 25 24 23 22 21
VCC 31
20 VCC
Q8 32
19 nQ3
nQ8 33
18 Q3
Q9 34
17 nQ2
nQ9 35
16 Q2
Q10 36
15 nQ1
nQ10 37
14 Q1
Q11 38
13 nQ0
nQ11 39
12 Q0
VCC 40
11 VCC
1 2 3 4 5 6 7 8 9 10
IDT8SLVP1212I
40-lead VFQFN
6mm x 6mm x 0.925mm package body,
2.9mm x 2.9mm E-Pad size
NL Package, Top View
IDT8SLVP1212ANLGI REVISION A JANUARY 28, 2014
1
©2014 Integrated Device Technology, Inc.