8SLVP1204 Datasheet, PDF (1/25 Pages) Integrated Device Technology – Maximum input clock frequency

Low Phase Noise, 2:4, 3.3V, 2.5V
LVPECL Output Fanout Buffer
8SLVP1204
DATA SHEET
General Description
The 8SLVP1204 is a high-performance differential LVPECL fanout
buffer. The device is designed for the fanout of high-frequency, very
low additive phase-noise clock and data signals. The 8SLVP1204 is
characterized to operate from a 3.3V or 2.5V power supply.
Guaranteed output-to-output and part-to-part skew characteristics
make the 8SLVP1204 ideal for those clock distribution applications
demanding well-defined performance and repeatability. Two
selectable differential inputs and four low skew outputs are available.
The integrated bias voltage reference enables easy interfacing of
single-ended signals to the device inputs. The device is optimized for
low power consumption and low additive phase noise.
Features
• Four low skew, low additive jitter LVPECL output pairs
• Two selectable, differential clock input pairs
• Differential PCLKx pairs can accept the following differential input
levels: LVDS, LVPECL, CML
• Differential PCLKx pairs can also accept single-ended LVCMOS
levels. See Section, “Applications Information”, section, “Wiring
the Differential Input to Accept Single-Ended Levels” (Figures 1A
and 1B)
• Maximum input clock frequency: 2GHz
• LVCMOS interface levels for the control input, (input select)
• Output skew: 5ps (typical), at 3.63V
• Propagation delay: 200ps (typical), at 3.63V
• Low additive phase jitter, RMS; f_REF = 156.25MHz, V_PP = 1V,
12kHz - 20MHz: 40fs (maximum), at 3.63V
• Maximum device current consumption (I_EE): 60mA (maximum),
at 3.63V
• Full 3.3V±5%, 3.3V±10% or 2.5V±5% supply
• Lead-free (RoHS 6), 16-Lead VFQFN packaging
• -40°C to 85°C ambient operating temperature
• Supports case temperature  105°C operations
Block Diagram
V_CC
PCLK0 ^Pulldown
nPCLK0 ^{Pullup/Pulldown}
V_CC
PCLK1 ^Pulldown
nPCLK1 ^{Pullup/Pulldown}
0 _fREF
1
SEL ^Pulldown
V_REF
Voltage
Reference
Pin Assignment
16 15 14 13
Q0
VEE 1
12 nQ1
nQ0
SEL 2
11 Q1
Q1
PCLK1 3
10 nQ0
nQ1
nPCLK1 4
9 Q0
5 6 78
Q2
nQ2
Q3
nQ3
8SLVP1204
16-Lead, 3mm x 3mm VFQFN Package
8SLVP1204 REVISION D 6/8/15
1
©2015 Integrated Device Technology, Inc.