8SLVD2102 Datasheet, PDF (1/18 Pages) Integrated Device Technology – Dual 1:2, LVDS Output Fanout Buffer

Dual 1:2, LVDS Output Fanout Buffer
8SLVD2102
DATA SHEET
General Description
The 8SLVD2102 is a high-performance differential dual 1:2 LVDS
fanout buffer. The device is designed for the fanout of high-frequency,
very low additive phase-noise clock and data signals. The
8SLVD2102 is characterized to operate from a 2.5V power supply.
Guaranteed output-to-output and part-to-part skew characteristics
make the 8SLVD2102 ideal for those clock distribution applications
demanding well-defined performance and repeatability. Two
independent buffers with two low skew outputs each are available.
The integrated bias voltage generators enables easy interfacing of
single-ended signals to the device inputs. The device is optimized for
low power consumption and low additive phase noise.
Features
• Two 1:2, low skew, low additive jitter LVDS fanout buffers
• Two differential clock inputs
• Differential pairs can accept the following differential input
levels: LVDS and LVPECL
• Maximum input clock frequency: 2GHz
• Output bank skew: 15ps (maximum)
• Propagation delay: 300ps (maximum)
• Low additive phase jitter: 200fs, RMS (maximum);
f_REF = 156.25MHz, V_PP = 1V, V_CMR = 1V,
Integration Range 10kHz - 20MHz
• 2.5V supply voltage
• Maximum device current consumption (I_DD): 90mA
• Lead-free (RoHS 6) 16-Lead VFQFN package
• -40°C to 85°C ambient operating temperature
Block Diagram
V_DD
PCLKA
nPCLKA
V_DD
PCLKB
nPCLKB
V_REF
EN
Voltage
V_DD ^Reference
QA0
nQA0
QA1
nQA1
QB0
nQB0
QB1
nQB1
Pin Assignment
16 15 14 13
GND ¹
12 nQA1
EN ²
PCLKB ³
8SLVD2102I
8XXXXXX
11 _QA1
10 nQA0
nPCLKB ⁴
9 QA0
5
6
7
8
16-pin, 3.0mm x 3.0mm VFQFN Package
8SLVD2102 REVISION 2 11/11/15
1
©2015 Integrated Device Technology, Inc.