8SLVD1212_16 Datasheet, PDF (1/21 Pages) Integrated Device Technology – 1:12, LVDS Output Fanout Buffer

1:12, LVDS Output Fanout Buffer
8SLVD1212
Datasheet
General Description
The 8SLVD1212 is a high-performance differential LVDS fanout
buffer. The device is designed for the fanout of high-frequency, very
low additive phase-noise clock and data signals. The 8SLVD1212 is
characterized to operate from a 2.5V power supply. Guaranteed
output-to-output and part-to-part skew characteristics make the
8SLVD1212 ideal for those clock distribution applications demanding
well-defined performance and repeatability. Two selectable
differential inputs and twelve low skew outputs are available. The
integrated bias voltage reference enables easy interfacing of
single-ended signals to the device inputs. The device is optimized for
low power consumption and low additive phase noise.
Features
• Twelve low skew, low additive jitter LVDS output pairs
• Two selectable, differential clock input pairs
• Differential PCLK, nPCLK pairs can accept the following
differential input levels: LVDS, LVPECL, CML
• Maximum input clock frequency: 2GHz (maximum)
• LVCMOS/LVTTL interface levels for the control input select pins
• Output skew: 45ps (max)
• Propagation delay: 310ps (typical)
• Low additive phase jitter, RMS; f_REF = 156.25MHz, 
10kHz - 20MHz: 77fs (typical)
• Maximum device current consumption (I_DD): 213mA
• 2.5V supply voltage
• Lead-free (RoHS 6), 40-Lead VFQFN packaging
• -40°C to 85°C ambient operating temperature
Pin Assignment
SEL
PCLK1
nPCLK1
VREF1
V_DD
V_DD
VREF0
nPCLK0
PCLK0
nc
40 39 38 37 36 35 34 33 32 31
1
30
2
29
3
28
4
27
5
8SLVD1212
26
6
25
7
24
8
23
9
22
10
21
11 12 13 14 15 16 17 18 19 20
GND
nQ7
Q7
nQ6
Q6
nQ5
Q5
nQ4
Q4
GND
40-Lead VFQFN
6.0mm x 6.0mm x 0.9mm package body
©2016 Integrated Device Technology, Inc.
1
Revision 3, July 5, 2016