8S89832I Datasheet, PDF (1/16 Pages) Integrated Device Technology – Low Skew, 1-to-4 Differential-to-LVDS Fanout Buffer

Low Skew, 1-to-4 Differential-to-LVDS
Fanout Buffer
8S89832I
Data Sheet
General Description
The 8S89832I is a high speed 1-to-4 Differential-to-LVDS Fanout
Buffer. The 8S89832I is optimized for high speed and very low output
skew, making it suitable for use in demanding applications such as
SONET, 1 Gigabit and 10 Gigabit Ethernet, and Fibre Channel. The
internally terminated differential input and VREF_AC pin allow other
differential signal families such as LVPECL, LVDS, and SSTL to be
easily interfaced to the input with minimal use of external
components. The device also has an output enable pin which may be
useful for system test and debug purposes. The 8S89832I is
packaged in a small 3mm x 3mm 16-pin VFQFN package which
makes it ideal for use in space-constrained applications.
Features
• Four differential LVDS output pairs
• IN, nIN input pairs can accept the following differential input levels:
LVPECL, LVDS, SSTL
• 50 internal input termination to V_T
• Maximum output frequency: 2GHz
• Output skew: 25ps (maximum)
• Part-to-part skew: 200ps (maximum)
• Propagation delay: 550ps (maximum)
• Additive phase jitter, RMS: 0.09ps (typical)
• Full 2.5V supply mode
• -40°C to 85°C ambient operating temperature
• Available in lead-free (RoHS 6) package
Block Diagram
IN
50Ω
V_T
50Ω
nIN
V_{REF_AC}
EN
DQ
CLK
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Pin Assignment
16 15 14 13
Q1 1
12 IN
nQ1 2
11 VT
Q2 3
10 VREF_AC
nQ2 4
9 nIN
5 6 78
8S89832I
16-Lead VFQFN
3mm x 3mm x 0.925mm package body
K Package
Top View
©2016 Integrated Device Technology, Inc
1
Revision A January 27, 2016