8P391208 Datasheet, PDF (1/41 Pages) Integrated Device Technology – Low Additive Jitter 2:8 Buffer with Universal Differential Outputs

Low Additive Jitter 2:8 Buffer with
Universal Differential Outputs
8P391208
Datasheet
General Description
8P391208 is intended to take 1 or 2 reference clocks, select
between them, using a pin selection and generate up to 8 outputs
that are the same as the reference frequency.
8P391208 supports two output banks, each with its own power
supply. All outputs in one bank would generate the same output
frequency, and each bank can be individually controlled for output
type or output enable.
The device can operate over the -40°C to +85°C temperature range.
Features
• Two differential inputs support LVPECL, LVDS, HCSL or LVCMOS
reference clocks
• Accepts input frequencies ranging from 1PPS (1Hz) to 700MHz
(up to 1GHz when configured into HCSL output mode at 3.3V)
• Select which of the two input clocks is to be used as the reference
clock for which bank via pin selection
• Generates 8 differential outputs
• Differential outputs selectable as LVPECL, LVDS, CML or HCSL
• CML mode supports two different voltage swings
• Differential outputs support frequencies from 1PPS to 700MHz
(up to 1GHz when configured into HCSL output mode at 3.3V)
• Outputs arranged in 2 banks of 4 outputs each
• Each bank supports a separate power supply of 3.3V, 2.5V or
1.8V
• Controlled by 3-level input pins
• Input mux selection control pin
• Control inputs are 3.3V-tolerant for all core voltages
• Output noise floor of -153dBc/Hz @ 156.25MHz
• Core voltage supply of 3.3V, 2.5V or 1.8V
• -40°C to +85°C ambient operating temperature
• Lead-free (RoHS 6) packaging
©2016 Integrated Device Technology
1
September 1, 2016