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8P34S2102 Datasheet, PDF (1/19 Pages) Integrated Device Technology – Dual 1:2 LVDS Output 1.8V Fanout Buffer | |||
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Dual 1:2 LVDS Output 1.8V Fanout Buffer
8P34S2102
Datasheet
Description
The 8P34S2102 is a high-performance, low-power, differential
dual 1:2 LVDS output, 1.8V fanout buffer. The device is designed
for the fanout of high-frequency, very low additive phase-noise
clock and data signals. Two independent buffer channels are
available. Each channel has two low-skew outputs. High isolation
between channels minimizes noise coupling. AC characteristics
such as propagation delay are matched between channels.
Guaranteed output-to-output and part-to-part skew characteristics
make the 8P34S2102 ideal for those clock distribution
applications demanding well-defined performance and
repeatability. The device is characterized to operate from a 1.8V
power supply. The integrated bias voltage references enable easy
interfacing of AC-coupled signals to the device inputs.
Block Diagram
Features
⪠Dual 1:2 low skew, low additive jitter LVDS fanout buffers
⪠Matched AC characteristics across both channels
⪠High isolation between channels
⪠Low power consumption
⪠Both differential CLKA, nCLKA and CLKB, nCLKB inputs
accept LVDS, LVPECL and single-ended LVCMOS
levels
⪠Maximum input clock frequency: 2GHz
⪠Output amplitudes: 350mV, 500mV (selectable)
⪠Output bank skew: 8ps typical
⪠Output skew: 10ps typical
⪠Low additive phase jitter, RMS: 45fs typical
(fREF = 156.25MHz, 12kHz - 20MHz)
⪠Full 1.8V supply voltage mode
⪠Device current consumption (IDD): 76mA typical
⪠Lead-free (RoHS 6), 16-lead VFQFN packaging
⪠-40°C to 85°C ambient operating temperature
⪠Supports case temperature up to 105°C
VDD
51k
CLKA
nCLKA
51k 51k
QA0
nQA0
QA1
nQA1
VREF
Voltage
Reference
VDD
51k
CLKB
nCLKB
51k 51k
VDD
51k
SELA
8P34S2102 transistor count: 293
QB0
nQB0
QB1
nQB1
©2016 Integrated Device Technology, Inc.
1
October 20, 2016
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