89PES24N3 Datasheet, PDF (1/2 Pages) Integrated Device Technology – 24-Lane 3-Port PCI Express Switch

24-Lane 3-Port PCI Express®
Switch
89PES24N3
Product Brief
Device Overview
The 89HPES24N3 is a member of IDT’s PRECISE™ family of PCI
Express® bridging and switching solutions offering the next-generation
I/O interconnect standard. The PES24N3 is a 24-lane, 3-port peripheral
chip that performs PCI Express Base switching with a feature set opti-
mized for high performance applications such as servers, storage, and
communications/networking. It provides high-performance I/O connec-
tivity and switching functions between a PCI Express upstream port and
two downstream ports or peer-to-peer switching between downstream
ports.
Features
High Performance PCI Express Switch
x _{24 PCI Express lanes (2.5Gbps), 3 switch ports}
x _{12 GBps (96 Gbps) aggregate switching throughput}
x _{Low latency cut-through switch architecture}
x _{Supports 128 to 2048 byte maximum payload size}
x _{One virtual channel}
x _{Fully compliant with PCI Express Base specification}
Revision 1.0a
Flexible Architecture with
Numerous Configuration Options
x _{Automatic per port link width negotiation to x8, x4, x2 or x1}
x _{Port arbitration schemes utilizing round robin or weighted}
round robin algorithms
x _{Static lane reversal on all ports}
x _{Polarity inversion}
x _{Ability to load device configuration from serial EEPROM}
Legacy Support
x _{PCI compatible INTx emulation}
x _{Bus locking}
Highly Integrated Solution
x _{Integrates 24 2.5 Gbps embedded SerDes, 8B/10B encoder/}
decoder (no separate transceivers needed)
x _{Incorporates on-chip internal memory for packet buffering}
and queueing
x _{Requires no external components}
Reliability, Availability, and Serviceability (RAS)
Features
x _{Internal end-to-end parity protection on all TLPs ensures}
data integrity even in systems that do not implement end-to-
end CRC (ECRC)
x _{ECRC passed through}
x _{Supports PCI Express Native Hot-Plug}
– Compatible with Hot-Plug I/O expanders used on PC mother-
boards
x _{Hot-Swap capable I/O}
Block Diagram
Frame Buffer
3-Port Switch Core
Route Table
Port
Arbitration
Scheduler
Transaction Layer
Data Link Layer
Multiplexer / Demultiplexer
Phy
Phy
Phy
Logical Logical
Logical
Layer Layer
...
Layer
SerDes SerDes
SerDes
Transaction Layer
Data Link Layer
Multiplexer / Demultiplexer
Phy
Phy
Phy
Logical Logical
Logical
Layer Layer
...
Layer
SerDes SerDes
SerDes
Transaction Layer
Data Link Layer
Multiplexer / Demultiplexer
Phy
Phy
Phy
Logical Logical
Logical
Layer Layer
...
Layer
SerDes SerDes
SerDes
 2005 Integrated Device Technology, Inc.
24 PCI Express Lanes
x8 Upstream Port and Two x8 Downstream Ports
Figure 1 Internal Block Diagram
IDT and the IDT logo are trademarks of Integrated Device Technology, Inc.
1 of 2
December 22, 2005
DSC 6803