89HPES8T5A Datasheet, PDF (1/29 Pages) Integrated Device Technology – 8-Lane 5-Port PCI Express Switch

8-Lane 5-Port
PCI Express® Switch
®
89HPES8T5A
Data Sheet
Advance Information*
Device Overview
The 89HPES8T5A is a member of IDT’s PRECISE™ family of PCI
Express switching solutions. The PES8T5A is an 8-lane, 5-port periph-
eral chip that performs PCI Express Base switching. It provides connec-
tivity and switching functions between a PCI Express upstream port and
up to four downstream ports and supports switching between down-
stream ports.
Features
◆ _{High Performance PCI Express Switch}
– Eight 2.5Gbps PCI Express lanes
– Five switch ports
– Upstream port is x4
– Downstream ports are x1
– Low-latency cut-through switch architecture
– Support for Max Payload Sizes up to 256 bytes
– One virtual channel
– Eight traffic classes
– PCI Express Base Specification Revision 1.1 compliant
◆ _{Flexible Architecture with Numerous Configuration Options}
– Automatic lane reversal on all ports
– Automatic polarity inversion on all lanes
– Ability to load device configuration from serial EEPROM
◆ _{Legacy Support}
– PCI compatible INTx emulation
– Bus locking
◆ _{Highly Integrated Solution}
– Requires no external components
– Incorporates on-chip internal memory for packet buffering and
queueing
– Integrates eight 2.5 Gbps embedded SerDes with 8B/10B
encoder/decoder (no separate transceivers needed)
◆ _{Reliability, Availability, and Serviceability (RAS) Features}
– Internal end-to-end parity protection on all TLPs ensures data
integrity even in systems that do not implement end-to-end
CRC (ECRC)
– Supports ECRC and Advanced Error Reporting
– Supports PCI Express Native Hot-Plug, Hot-Swap capable I/O
– Compatible with Hot-Plug I/O expanders used on PC mother-
boards
◆ _{Power Management}
– Utilizes advanced low-power design techniques to achieve low
typical power consumption
– Supports PCI Power Management Interface specification (PCI-
PM 1.2)
– Unused SerDes are disabled.
– Supports Advanced Configuration and Power Interface Speci-
fication, Revision 2.0 (ACPI) supporting active link state
◆ _{Testability and Debug Features}
– Built in Pseudo-Random Bit Stream (PRBS) generator
– Numerous SerDes test modes
– Ability to read and write any internal register via the SMBus
– Ability to bypass link training and force any link into any mode
– Provides statistics and performance counters
Block Diagram
Frame Buffer
5-Port Switch Core / 8 PCI Express Lanes
Route Table
Port
Arbitration
Scheduler
Transaction Layer
Data Link Layer
Mux / Demux
Phy
Logical
Layer
SerDes
Transaction Layer
Data Link Layer
Mux / Demux
Phy
Logical
Layer
SerDes
Transaction Layer
Data Link Layer
Mux / Demux
Phy
Logical
Layer
SerDes
Transaction Layer
Data Link Layer
Mux / Demux
Phy
Logical
Layer
SerDes
Transaction Layer
Data Link Layer
Mux / Demux
Phy
Logical
Layer
SerDes
(Port 0)
(Port 2)
(Port 3)
Figure 1 Internal Block Diagram
(Port 4)
© 2007 Integrated Device Technology, Inc.
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
1 of 29
*Notice: The information in this document is subject to change without notice
(Port 5)
September 7, 2007