89HPES8NT2 Datasheet, PDF (1/3 Pages) Integrated Device Technology – 8-Lane 2-Port Non-Transparent PCI Express® Switch

8-Lane 2-Port Non-Transparent
PCI Express® Switch
89HPES8NT2
Product Brief
Device Overview
The 89HPES8NT2 is a member of the IDT PRECISE™ family of PCI
Express® switching solutions offering the next-generation I/O intercon-
nect standard. The PES8NT2 is a 8-lane, 2-port peripheral chip that
provides high-performance switching and non-transparent bridging
(NTB) functions between a PCIe® upstream port and an NTB down-
stream port. The PES8NT2 is a part of the IDT PCIe System Intercon-
nect Products and is intended to be used with IDT PCIe System
Interconnect Switches. Together, the chipset targets multi-host and intel-
ligent I/O applications such as communications, storage, and blade
servers where inter-domain communication is required.
Features
◆ _{High Performance PCI Express Switch}
– Eight PCI Express lanes (2.5Gbps), two switch ports
– Delivers 32 Gbps (4 GBps) of aggregate switching capacity
– Low latency cut-through switch architecture
– Support for Max Payload size up to 2048 bytes
– Supports one virtual channel and eight traffic classes
– PCI Express Base specification Revision 1.0a compliant
◆ _{Flexible Architecture with Numerous Configuration Options}
– Supports automatic per port link width negotiation (x8, x4, x2,
or x1)
– Static lane reversal on all ports
– Automatic polarity inversion on all lanes
– Supports locked transactions, allowing use with legacy soft-
ware
Block Diagram
– Ability to load device configuration from serial EEPROM
– Ability to control device via SMBus
◆ _{Non-Transparent Port}
– Crosslink support on NTB port
– Four mapping windows supported
• Each may be configured as a 32-bit memory or I/O window
• May be paired to form a 64-bit memory window
– Interprocessor communication
• Thirty-two inbound and outbound doorbells
• Four inbound and outbound message registers
• Two shared scratchpad registers
– Allows up to sixteen masters to communicate through the non-
transparent port
– No limit on the number of supported outstanding transactions
through the non-transparent bridge
– Completely symmetric non-transparent bridge operation
allows similar/same configuration software to be run
– Supports direct connection to a transparent or non-transparent
port of another switch
◆ _{Highly Integrated Solution}
– Requires no external components
– Incorporates on-chip internal memory for packet buffering and
queueing
– Integrates eight 2.5 Gbps embedded full duplex SerDes, 8B/
10B encoder/decoder (no separate transceivers needed)
Frame Buffer
2-Port Switch Core
Route Table
Port
Arbitration
Scheduler
Transaction Layer
Data Link Layer
Multiplexer / Demultiplexer
Phy
Phy
Phy
Logical Logical
Logical
Layer Layer
...
Layer
SerDes SerDes
SerDes
Transaction Layer
Data Link Layer
Non-
Transparent
Bridge
Multiplexer / Demultiplexer
Phy
Phy
Phy
Logical Logical
Logical
Layer Layer
...
Layer
SerDes SerDes
SerDes
© 2007 Integrated Device Technology, Inc.
8 PCI Express Lanes
x4 Upstream Port and One x4 Downstream Port
Figure 1 Internal Block Diagram
IDT and the IDT logo are trademarks of Integrated Device Technology, Inc.
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March 14, 2007