89HPES4T4G2 Datasheet, PDF (1/30 Pages) Integrated Device Technology – Support for Max Payload Size up to 2Kbytes

4-Lane 4-Port
Gen2 PCI Express® Switch
®
89HPES4T4G2
Data Sheet
Device Overview
The 89HPES4T4G2, a 4-lane 4-port Gen2 PCI Express® switch, is a
member of IDT’s PRECISE™ family of PCI Express switching solutions.
The PES4T4G2 is a peripheral chip that performs PCI Express base
switching with a feature set optimized for servers, storage, communica-
tions, and consumer applications. It provides connectivity and switching
functions between a PCI Express upstream port and three downstream
ports or peer-to-peer switching between downstream ports.
Features
 _{High Performance PCI Express Switch}
– Four Gen2 PCI Express lanes supporting 5 Gbps and
2.5 Gbps operations
– Four switch ports
• One x1 upstream port
• Three x1 downstream ports
– Low latency cut-through switch architecture
– Support for Max Payload Size up to 2Kbytes
– Supports one virtual channel and eight traffic classes
– PCI Express Base Specification Revision 2.0 compliant
 _{Flexible Architecture with Numerous Configuration Options}
– Automatic lane reversal on all ports
– Automatic polarity inversion
– Ability to load device configuration from serial EEPROM
 _{Legacy Support}
– PCI compatible INTx emulation
– Bus locking
 _{Highly Integrated Solution}
– Requires no external components
– Incorporates on-chip internal memory for packet buffering and
queueing
– Integrates four 5 Gbps embedded SerDes with 8b/10b
encoder/decoder (no separate transceivers needed)
• Receive equalization (RxEQ)
 _{Reliability, Availability, and Serviceability (RAS) Features}
– Internal end-to-end parity protection on all TLPs ensures data
integrity even in systems that do not implement end-to-end
CRC (ECRC)
– Supports ECRC and Advanced Error Reporting
– All internal data and control RAMs are SECDED ECC
protected
– Supports PCI Express Native Hot-Plug, Hot-Swap capable I/O
– Compatible with Hot-Plug I/O expanders used on PC mother-
boards
– Supports Hot-Swap
Block Diagram
Frame Buffer
4-Port Switch Core / 4 Gen2 PCI Express Lanes
Route Table
Port
Arbitration
Scheduler
Transaction Layer
Data Link Layer
Mux / Demux
Phy
Logical
Layer
SerDes
Transaction Layer
Data Link Layer
Mux / Demux
Phy
Logical
Layer
SerDes
Transaction Layer
Data Link Layer
Mux / Demux
Phy
Logical
Layer
SerDes
Transaction Layer
Data Link Layer
Mux / Demux
Phy
Logical
Layer
SerDes
(Port 0)
(Port 1)
(Port 2)
(Port 3)
Figure 1 Internal Block Diagram
 2013 Integrated Device Technology, Inc.
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
1 of 30
May 23, 2013
DSC 6928