89HPES48H12 Datasheet, PDF (1/48 Pages) Integrated Device Technology – 48-Lane 12-Port PCI Express System Interconnect Switch

48-Lane 12-Port PCI Express®
System Interconnect Switch
®
89HPES48H12
Data Sheet
Device Overview
The 89HPES48H12 is a member of the IDT PRECISE™ family of
PCI Express® switching solutions. The PES48H12 is a 48-lane, 12-port
system interconnect switch optimized for PCI Express packet switching
in high-performance applications, supporting multiple simultaneous
peer-to-peer traffic flows. Target applications include servers, storage,
communications, and embedded systems.
Features
◆ _{High Performance PCI Express Switch}
– Twelve maximum switch ports
• Six main ports each of which consists of 8 SerDes
• Each x8 main port can further bifurcate to 2 x4-ports
– Forty-eight 2.5 Gbps embedded SerDes
• Supports pre-emphasis and receive equalization on per-port
basis
– Delivers 192 Gbps (24 GBps) of aggregate switching capacity
– Low-latency cut-through switch architecture
– Support for Max Payload Size up to 2048 bytes
– Supports two virtual channels and eight traffic classes
– PCI Express Base Specification Revision 1.1 compliant
◆ _{Flexible Architecture with Numerous Configuration Options}
– Port arbitration schemes utilizing round robin algorithms
– Virtual channels arbitration based on priority
– Automatic per port link width negotiation to x8, x4, x2 or x1
– Supports automatic lane reversal on all ports
– Supports automatic polarity inversion on all lanes
– Supports locked transactions, allowing use with legacy soft-
ware
– Ability to load device configuration from serial EEPROM
– Ability to control device via SMBus
◆ _{Highly Integrated Solution}
– Requires no external components
– Incorporates on-chip internal memory for packet buffering and
queueing
– Integrates forty-eight 2.5 Gbps embedded full duplex SerDes,
8B/10B encoder/decoder (no separate transceivers needed)
◆ _{Reliability, Availability, and Serviceability (RAS) Features}
– Redundant upstream port failover capability
– Supports optional PCI Express end-to-end CRC checking
– Internal end-to-end parity protection on all TLPs ensures data
integrity even in systems that do not implement end-to-end
CRC (ECRC)
Block Diagram
x8/x4/x2/x1
x8/x4/x2/x1
x8/x4/x2/x1
SerDes
DL/Transaction Layer
SerDes
DL/Transaction Layer
SerDes
DL/Transaction Layer
Route Table
Frame Buffer
12-Port Switch Core
Port
Arbitration
Scheduler
DL/Transaction Layer
SerDes
DL/Transaction Layer
SerDes
DL/Transaction Layer
SerDes
x8/x4/x2/x1
x8/x4/x2/x1
x8/x4/x2/x1
© 2007 Integrated Device Technology, Inc.
48 PCI Express Lanes
Up to 6 x8 ports or 12 x4 Ports
Figure 1 Internal Block Diagram
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
1 of 48
July 19, 2007
DSC 6925