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89HPES32T8G2 Datasheet, PDF (1/39 Pages) Integrated Device Technology – Low latency cut-through architecture | |||
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32-Lane 8-Port PCIe® Gen2
I/O Expansion Switch
®
89HPES32T8G2
Data Sheet
Device Overview
The 89HPES32T8G2 is a member of the IDT PRECISE⢠family of
PCI Express® switching solutions. The PES32T8G2 is a 32-lane, 8-port
switch optimized for PCI Express Gen2 packet switching in high-perfor-
mance applications. Target applications include servers, storage,
communications, embedded systems, and multi-host or intelligent I/O
based systems with inter-domain communication.
Features
ïµ High Performance Non-Blocking Switch Architecture
â 32-lane 8-port PCIe switch
⢠Four x8 switch ports each of which can bifurcate to two x4
ports (total of eight x4 ports)
â Integrated SerDes supports 5.0 GT/s Gen2 and 2.5 GT/s
Gen1 operation
â Delivers up to 32 GBps (256 Gbps) of switching capacity
â Supports 128 Bytes to 2 KB maximum payload size
â Low latency cut-through architecture
â Supports one virtual channel and eight traffic classes
ïµ Standards and Compatibility
â PCI Express Base Specification 2.0 compliant
â Implements the following optional PCI Express features
⢠Advanced Error Reporting (AER) on all ports
⢠End-to-End CRC (ECRC)
⢠Access Control Services (ACS)
⢠Power Budgeting Enhanced Capability
⢠Device Serial Number Enhanced Capability
⢠Sub-System ID and Sub-System Vendor ID Capability
⢠Internal Error Reporting ECN
⢠Multicast ECN
⢠VGA and ISA enable
⢠L0s and L1 ASPM
⢠ARI ECN
ïµ Port Configurability
â x4 and x8 ports
⢠Ability to merge adjacent x4 ports to create a x8 port
â Automatic per port link width negotiation
(x8 â x4 â x2 â x1)
â Crosslink support
â Automatic lane reversal
â Autonomous and software managed link width and speed
control
â Per lane SerDes configuration
⢠De-emphasis
⢠Receive equalization
⢠Drive strength
ïµ Initialization / Configuration
â Supports Root (BIOS, OS, or driver), Serial EEPROM, or
SMBus switch initialization
â Common switch configurations are supported with pin strap-
ping (no external components)
â Supports in-system Serial EEPROM initialization/program-
ming
ïµ Quality of Service (QoS)
â Port arbitration
⢠Round robin
â Request metering
⢠IDT proprietary feature that balances bandwidth among
switch ports for maximum system throughput
â High performance switch core architecture
⢠Combined Input Output Queued (CIOQ) switch architecture
with large buffers
ïµ Multicast
â Compliant to the PCI-SIG multicast ECN
â Supports arbitrary multicasting of Posted transactions
â Supports 64 multicast groups
â Multicast overlay mechanism support
â ECRC regeneration support
ïµ Clocking
â Supports 100 MHz and 125 MHz reference clock frequencies
â Flexible clocking modes
⢠Common clock
⢠Non-common clock
ïµ Hot-Plug and Hot Swap
â Hot-plug controller on all ports
⢠Hot-plug supported on all downstream switch ports
â All ports support hot-plug using low-cost external I2C I/O
expanders
â Configurable presence detect supports card and cable appli-
cations
â GPE output pin for hot-plug event notification
⢠Enables SCI/SMI generation for legacy operating system
support
â Hot-swap capable I/O
ïµ Power Management
â Supports D0, D3hot and D3 power management states
â Active State Power Management (ASPM)
⢠Supports L0, L0s, L1, L2/L3 Ready and L3 link states
⢠Configurable L0s and L1 entry timers allow performance/
power-savings tuning
ï£ 2011 Integrated Device Technology, Inc.
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
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November 28, 2011
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