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89HPES32NT8AG2 Datasheet, PDF (1/35 Pages) Integrated Device Technology – Supports 128 Bytes to 2 KB maximum payload size | |||
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32-Lane 8-Port PCIe® Gen2
System Interconnect Switch
®
89HPES32NT8AG2
Datasheet
Device Overview
The 89HPES32NT8AG2 is a member of the IDT family of PCI
Express® switching solutions. The PES32NT8AG2 is a 32-lane, 8-port
system interconnect switch optimized for PCI Express Gen2 packet
switching in high-performance applications, supporting multiple simulta-
neous peer-to-peer traffic flows. Target applications include multi-host or
intelligent I/O based systems where inter-domain communication is
required, such as servers, storage, communications, and embedded
systems.
Features
ïµ High Performance Non-Blocking Switch Architecture
â 32-lane, 8-port PCIe switch with flexible port configuration
â Integrated SerDes supports 5.0 GT/s Gen2 and 2.5 GT/s
Gen1 operation
â Delivers up to 32 GBps (256 Gbps) of switching capacity
â Supports 128 Bytes to 2 KB maximum payload size
â Low latency cut-through architecture
â Supports one virtual channel and eight traffic classes
ïµ Port Configurability
â Eight x4 switch ports
⢠Adjacent x4 ports can be merged to achieve x8 port widths
â Automatic per port link width negotiation
(x8 ï® x4 ï® x2 ï® x1)
â Crosslink support
â Automatic lane reversal
â Per lane SerDes configuration
⢠De-emphasis
⢠Receive equalization
⢠Drive strength
ïµ Innovative Switch Partitioning Feature
â Supports up to 8 fully independent switch partitions
â Logically independent switches in the same device
â Configurable downstream port device numbering
â Supports dynamic reconfiguration of switch partitions
⢠Dynamic port reconfiguration â downstream, upstream,
non-transparent bridge
⢠Dynamic migration of ports between partitions
⢠Movable upstream port within and between switch partitions
ïµ Non-Transparent Bridging (NTB) Support
â Supports up to 8 NT endpoints per switch, each endpoint can
communicate with other switch partitions or external PCIe
domains or CPUs
â 6 BARs per NT Endpoint
⢠Bar address translation
⢠All BARs support 32/64-bit base and limit address translation
⢠Two BARs (BAR2 and BAR4) support look-up table based
address translation
â 32 inbound and outbound doorbell registers
â 4 inbound and outbound message registers
â Supports up to 64 masters
â Unlimited number of outstanding transactions
ïµ Multicast
â Compliant with the PCI-SIG multicast
â Supports 64 multicast groups
â Supports multicast across non-transparent port
â Multicast overlay mechanism support
â ECRC regeneration support
ïµ Integrated Direct Memory Access (DMA) Controllers
â Supports up to 2 DMA upstream ports, each with 2 DMA chan-
nels
â Supports 32-bit and 64-bit memory-to-memory transfers
⢠Fly-by translation provides reduced latency and increased
performance over buffered approach
⢠Supports arbitrary source and destination address alignment
⢠Supports intra- as well as inter-partition data transfers using
the non-transparent endpoint
â Supports DMA transfers to multicast groups
â Linked list descriptor-based operation
â Flexible addressing modes
⢠Linear addressing
⢠Constant addressing
ïµ Quality of Service (QoS)
â Port arbitration
⢠Round robin
â Request metering
⢠IDT proprietary feature that balances bandwidth among
switch ports for maximum system throughput
â High performance switch core architecture
⢠Combined Input Output Queued (CIOQ) switch architecture
with large buffers
ïµ Clocking
â Supports 100 MHz and 125 MHz reference clock frequencies
â Flexible port clocking modes
⢠Common clock
⢠Non-common clock
⢠Local port clock with SSC (spread spectrum setting) and port
reference clock input
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
ï£ 2013 Integrated Device Technology, Inc
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December 17, 2013
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