89HPES32H8 Datasheet, PDF (1/40 Pages) Integrated Device Technology – 32-Lane 8-Port PCI Express System Interconnect Switch

32-Lane 8-Port PCI Express®
System Interconnect Switch
®
89HPES32H8
Data Sheet
Device Overview
The 89HPES32H8 is a member of the IDT PRECISE™ family of PCI
Express® switching solutions. The PES32H8 is a 32-lane, 8-port system
interconnect switch optimized for PCI Express packet switching in high-
performance applications, supporting multiple simultaneous peer-to-
peer traffic flows. Target applications include servers, storage, communi-
cations, and embedded systems.
Features
◆ _{High Performance PCI Express Switch}
– Eight maximum switch ports
• Four main ports each of which consists of eight SerDes
• Each x8 main port can further bifurcate to 2 x4-ports
– Thirty-two 2.5 Gbps embedded SerDes
• Supports pre-emphasis and receive equalization on per-port
basis
– Delivers 128 Gbps (16 GBps) aggregate switching capacity
– Low-latency cut-through switch architecture
– Support for Max Payload Size up to 2048 bytes
– Supports two virtual channels and eight traffic classes
– PCI Express Base Specification Revision 1.1 compliant
◆ _{Flexible Architecture with Numerous Configuration Options}
– Port arbitration schemes utilizing round robin algorithms
– Virtual channels arbitration based on priority
– Automatic per port link width negotiation to x8, x4, x2 or x1
– Automatic lane reversal on all ports
– Automatic polarity inversion on all ports
– Supports locked transactions, allowing use with legacy soft-
ware
– Ability to load device configuration from serial EEPROM
– Ability to control device via SMBus
◆ _{Highly Integrated Solution}
– Requires no external components
– Incorporates on-chip internal memory for packet buffering and
queueing
– Integrates thirty-two 2.5 Gbps embedded full duplex SerDes,
8B/10B encoder/decoder (no separate transceivers needed)
◆ _{Reliability, Availability, and Serviceability (RAS) Features}
– Redundant upstream port failover capability
– Internal end-to-end parity protection on all TLPs ensures data
integrity even in systems that do not implement end-to-end
CRC (ECRC)
Block Diagram
x8/x4/x2/x1
SerDes
DL/Transaction Layer
x8/x4/x2/x1
SerDes
DL/Transaction Layer
Route Table
Frame Buffer
8-Port Switch Core
Port
Arbitration
Scheduler
DL/Transaction Layer
SerDes
DL/Transaction Layer
SerDes
x8/x4/x2/x1
x8/x4/x2/x1
Figure 1 Internal Block Diagram
© 2007 Integrated Device Technology, Inc.
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
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July 19, 2007