89HPES24N3 Datasheet, PDF (1/30 Pages) Integrated Device Technology – Supports one virtual channel

24-Lane 3-Port PCI Express®
Switch
89HPES24N3
Data Sheet
Device Overview
The 89HPES24N3 is a member of IDT’s PRECISE™ family of PCI
Express® switching solutions offering the next-generation I/O intercon-
nect standard. The PES24N3 is a 24-lane, 3-port peripheral chip that
performs PCI Express Base switching with a feature set optimized for
high performance applications such as servers, storage, and communi-
cations/networking. It provides high-performance I/O connectivity and
switching functions between a PCIe® upstream port and two down-
stream ports or peer-to-peer switching between downstream ports.
Features
◆ _{High Performance PCI Express Switch}
– 24 PCI Express lanes (2.5Gbps), 3 switch ports
– Delivers 12 GBps (96 Gbps) aggregate switching capacity
– Low latency cut-through switch architecture
– Supports 128 to 2048 byte maximum payload size
– Supports one virtual channel
– PCI Express Base specification Revision 1.0a compliant
◆ _{Flexible Architecture with Numerous Configuration Options}
– Port arbitration schemes utilizing round robin or weighted
round robin algorithms
– Supports automatic per port link with negotiation (x8, x4, x2, or
x1)
– Supports static lane reversal on all ports
– Supports polarity inversion
– Supports locked transactions, allowing use with legacy soft-
ware
– Ability to load device configuration from serial EEPROM
◆ _{Highly Integrated Solution}
– Requires no external components
– Incorporates on-chip internal memory for packet buffering and
queueing
– Integrates 24 2.5 Gbps embedded SerDes, 8B/10B encoder/
decoder (no separate transceivers needed)
◆ _{Reliability, Availability, and Serviceability (RAS) Features}
– Internal end-to-end parity protection on all TLPs ensures data
integrity even in systems that do not implement end-to-end
CRC (ECRC)
– Supports ECRC passed through
– Supports PCI Express Native Hot-Plug
• Compatible with Hot-Plug I/O expanders used on PC moth-
erboards
– Supports Hot-Swap
◆ _{Power Management}
– Supports PCI Express Power Management Interface specifi-
cation, Revision 1.1 (PCI-PM)
– Unused SerDes are disabled
– Supports Advanced Configuration and Power Interface Speci-
fication, Revision 2.0 (ACPI) supporting active link state
◆ _{Testability and Debug Features}
– Built in SerDes Pseudo-Random Bit Stream (PRBS) generator
– Ability to read and write any internal register via the SMBus
Block Diagram
Frame Buffer
3-Port Switch Core
Route Table
Port
Arbitration
Scheduler
Transaction Layer
Data Link Layer
Multiplexer / Demultiplexer
Phy
Phy
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Logical Logical
Logical
Layer Layer
...
Layer
SerDes SerDes
SerDes
Transaction Layer
Data Link Layer
Multiplexer / Demultiplexer
Phy
Phy
Phy
Logical Logical
Logical
Layer Layer
...
Layer
SerDes SerDes
SerDes
Transaction Layer
Data Link Layer
Multiplexer / Demultiplexer
Phy
Phy
Phy
Logical Logical
Logical
Layer Layer
...
Layer
SerDes SerDes
SerDes
© 2006 Integrated Device Technology, Inc.
24 PCI Express Lanes
x8 Upstream Port and Two x8 Downstream Ports
Figure 1 Internal Block Diagram
IDT and the IDT logo are trademarks of Integrated Device Technology, Inc.
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July 18, 2006
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