89HPES16T7 Datasheet, PDF (1/2 Pages) Integrated Device Technology – 16-Lane 7-Port PCI Express® Switch

16-Lane 7-Port
PCI Express® Switch
89HPES16T7
Product Brief
Device Overview
The 89HPES16T7 is a member of the IDT PRECISE™ family of PCI
Express switching solutions. The PES16T7 is a 16-lane, 7-port periph-
eral chip that performs PCI Express Packet switching with a feature set
optimized for high performance applications such as servers, storage
and communications/networking. It provides connectivity and switching
functions between a PCI Express upstream port and up to seven down-
stream ports and supports switching between downstream ports.
Features
◆ _{High Performance PCI Express Switch}
– Sixteen 2.5 Gbps PCI Express lanes
– Seven switch ports
– Upstream port configurable up to x8
– Two downstream ports configurable up to x4, four downstream
ports are x1
– Low-latency cut-through switch architecture
– Support for Max Payload Sizes up to 2048 bytes
– One virtual channel
– Eight traffic classes
– PCI Express Base Specification Revision 1.1 compliant
◆ _{Flexible Architecture with Numerous Configuration Options}
– Automatic per port link width negotiation to x8, x4, x2 or x1
– Automatic lane reversal on all ports
– Automatic polarity inversion on all lanes
– Ability to load device configuration from serial EEPROM
◆ _{Legacy Support}
– PCI compatible INTx emulation
– Bus locking
◆ _{Highly Integrated Solution}
– Requires no external components
– Incorporates on-chip internal memory for packet buffering and
queueing
– Integrates sixteen 2.5 Gbps embedded SerDes with 8B/10B
encoder/decoder (no separate transceivers needed)
◆ _{Reliability, Availability, and Serviceability (RAS) Features}
– Supports ECRC and Advanced Error Reporting
– Internal end-to-end parity protection on all TLPs ensures data
integrity even in systems that do not implement end-to-end
CRC (ECRC)
– Supports PCI Express Native Hot-Plug, Hot-Swap capable I/O
– Compatible with Hot-Plug I/O expanders used on PC and
server motherboards
◆ _{Power Management}
– Utilizes advanced low-power design techniques to achieve low
typical power consumption
– Supports PCI Power Management Interface specification (PCI-
PM 1.1)
• Supports device power management states: D0, D3_hot and
D3_cold
– Unused SerDes are disabled
Block Diagram
Frame Buffer
7-Port Switch Core / 16 PCI Express Lanes
Route Table
Port
Arbitration
Scheduler
Transaction Layer
Data Link Layer
Multiplexer / Demultiplexer
Transaction Layer
Data Link Layer
Multiplexer / Demultiplexer
Transaction Layer
Data Link Layer
Multiplexer / Demultiplexer
Phy
Logical
Layer
SerDes
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SerDes
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SerDes
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SerDes
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SerDes
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SerDes
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SerDes
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SerDes
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SerDes
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Logical
Layer
SerDes
TL
DLL
Mux/Demux
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Layer
SerDes
TL
DLL
Mux/Demux
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Logical
Layer
SerDes
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© 2007 Integrated Device Technology, Inc.
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Figure 1 Internal Block Diagram
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
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February 8, 2007