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89HPES16T4G2 Datasheet, PDF (1/32 Pages) Integrated Device Technology – 16-Lane 4-Port Gen2 PCI Express Switch | |||
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16-Lane 4-Port
Gen2 PCI Express® Switch
®
89HPES16T4G2
Data Sheet
Advance Information*
Device Overview
The 89HPES16T4G2 is a member of IDTâs PRECISE⢠family of PCI
Express® switching solutions. The PES16T4G2 is a 16-lane, 4-port
Gen2 peripheral chip that performs PCI Express Base switching with a
feature set optimized for high performance applications such as servers,
storage, and communications/networking. It provides connectivity and
switching functions between a PCI Express upstream port and up to
three downstream ports and supports switching between downstream
ports.
Features
â High Performance PCI Express Switch
â Sixteen 5 Gbps Gen2 PCI Express lanes
â Four switch ports
⢠One x4 upstream port
⢠Three x4 downstream ports
â Low latency cut-through switch architecture
â Support for Max Payload Size up to 2048 bytes
â One virtual channel
â Eight traffic classes
â PCI Express Base Specification Revision 2.0 compliant
â Flexible Architecture with Numerous Configuration Options
â Automatic per port link width negotiation to x4, x2 or x1
â Automatic lane reversal on all ports
â Automatic polarity inversion
â Ability to load device configuration from serial EEPROM
â Legacy Support
â PCI compatible INTx emulation
â Bus locking
â Highly Integrated Solution
â Incorporates on-chip internal memory for packet buffering and
queueing
â Integrates sixteen 5 Gbps embedded SerDes with 8b/10b
encoder/decoder (no separate transceivers needed)
⢠Receive equalization (RxEQ)
â Reliability, Availability, and Serviceability (RAS) Features
â Internal end-to-end parity protection on all TLPs ensures data
integrity even in systems that do not implement end-to-end
CRC (ECRC)
â Supports ECRC and Advanced Error Reporting
â Supports PCI Express Native Hot-Plug, Hot-Swap capable I/O
â Compatible with Hot-Plug I/O expanders used on PC mother-
boards
â Supports Hot-Swap
Block Diagram
Frame Buffer
4-Port Switch Core / 16 PCI Express Lanes
Route Table
Port
Arbitration
Scheduler
Transaction Layer
Data Link Layer
Multiplexer / Demultiplexer
Phy
Logical
Layer
SerDes
Transaction Layer
Data Link Layer
Multiplexer / Demultiplexer
Phy
Logical
Layer
SerDes
Transaction Layer
Data Link Layer
Multiplexer / Demultiplexer
Phy
Logical
Layer
SerDes
Transaction Layer
Data Link Layer
Multiplexer / Demultiplexer
Phy
Logical
Layer
SerDes
(Port 0)
(Port 2)
(Port 4)
Figure 1 Internal Block Diagram
© 2007 Integrated Device Technology, Inc.
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
1 of 32
*Notice: The information in this document is subject to change without notice
(Port 6)
September 4, 2007
DSC 6928
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