89HPES10T4G2 Datasheet, PDF (1/30 Pages) Integrated Device Technology – One virtual channel

10-Lane 4-Port
Gen2 PCI Express® Switch
®
89HPES10T4G2
Data Sheet
Device Overview
The 89HPES10T4G2 is a member of IDT’s PRECISE™ family of PCI
Express® switching solutions. The PES10T4G2 is a 10-lane, 4-port
Gen2 peripheral chip that performs PCI Express Base switching with a
feature set optimized for high performance applications such as servers,
storage, and communications/networking. It provides connectivity and
switching functions between a PCI Express upstream port and two
downstream ports and supports switching between downstream ports.
Features
◆ _{High Performance PCI Express Switch}
– Ten 5 Gbps Gen2 PCI Express lanes
– Four switch ports
• One x4 upstream port
• Three x2 downstream ports
– Low latency cut-through switch architecture
– Support for Max Payload Size up to 2048 bytes
– One virtual channel
– Eight traffic classes
– PCI Express Base Specification Revision 2.0 compliant
◆ _{Flexible Architecture with Numerous Configuration Options}
– Automatic per port link width negotiation to x4, x2 or x1
– Automatic lane reversal on all ports
– Automatic polarity inversion
– Ability to load device configuration from serial EEPROM
Block Diagram
◆ _{Legacy Support}
– PCI compatible INTx emulation
– Bus locking
◆ _{Highly Integrated Solution}
– Incorporates on-chip internal memory for packet buffering and
queueing
– Integrates ten 5 Gbps embedded SerDes with 8b/10b
encoder/decoder (no separate transceivers needed)
• Receive equalization (RxEQ)
◆ _{Reliability, Availability, and Serviceability (RAS) Features}
– Internal end-to-end parity protection on all TLPs ensures data
integrity even in systems that do not implement end-to-end
CRC (ECRC)
– Supports ECRC and Advanced Error Reporting
– Supports PCI Express Native Hot-Plug, Hot-Swap capable I/O
– Compatible with Hot-Plug I/O expanders used on PC mother-
boards
– Supports Hot-Swap
Frame Buffer
4-Port Switch Core / 10 PCI Express Lanes
Route Table
Port
Arbitration
Scheduler
Transaction Layer
Data Link Layer
Multiplexer / Demultiplexer
Phy
Logical
Layer
SerDes
Transaction Layer
Data Link Layer
Multiplexer / Demultiplexer
Phy
Logical
Layer
SerDes
Transaction Layer
Data Link Layer
Multiplexer / Demultiplexer
Phy
Logical
Layer
SerDes
Transaction Layer
Data Link Layer
Multiplexer / Demultiplexer
Phy
Logical
Layer
SerDes
(Port 0)
(Port 2)
(Port 4)
Figure 1 Internal Block Diagram
 2011 Integrated Device Technology, Inc.
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
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(Port 6)
August 10, 2011
DSC 6930