87973I-147 Datasheet, PDF (1/19 Pages) Integrated Device Technology – Fully integrated PLL

Low Skew, 1-to-12 LVCMOS/ LVTTL Clock
Multiplier/ Zero Delay Buffer
87973I-147
DATA SHEET
General Description
The 87973I-147 is a LVCMOS/LVTTL clock generator. The
87973I-147 has three selectable inputs and provides 14
LVCMOS/LVTTL outputs.
The 87973I-147 is a highly flexible device. The three selectable
inputs (1 differential and 2 single ended inputs) are often used in
systems requiring redundant clock sources. Up to three different
output frequencies can be generated among the three output banks.
The three output banks and feedback output each have their own
output dividers which allows the device to generate a multitude of
different bank frequency ratios and output-to-input frequency ratios.
In addition, 2 outputs in Bank C (QC2, QC3) can be selected to be
inverting or non-inverting. The output frequency range is 10MHz to
150MHz. The input frequency range is 6MHz to 120MHz.
The 87973I-147 also has a QSYNC output which can be used for
system synchronization purposes. It monitors Bank A and Bank C
outputs and goes low one period prior to coincident rising edges of
Bank A and Bank C clocks. QSYNC then goes high again when the
coincident rising edges of Bank A and Bank C occur. This feature is
used primarily in applications where Bank A and Bank C are running
at different frequencies, and is particularly useful when they are
running at non-integer multiples of one another.
Example Applications:
1.System Clock generator: Use a 16.66MHz reference clock to
generate eight 33.33MHz copies for PCI and four 100MHz copies
for the CPU or PCI-X.
2.Line Card Multiplier: Multiply differential 62.5MHz from a back
plane to single-ended 125MHz for the line Card ASICs and Gigabit
Ethernet Serdes.
3.Zero Delay buffer for Synchronous memory: Fanout up to twelve
100MHz copies from a memory controller reference clock to the
memory chips on a memory module with zero delay.
Features
• Fully integrated PLL
• Fourteen LVCMOS/LVTTL outputs to include: twelve clocks,
one feedback, one sync
• Selectable differential CLK, nCLK inputs or LVCMOS/LVTTL
reference clock inputs
• CLK0, CLK1 can accept the following input levels:
LVCMOS or LVTTL
• CLK, nCLK pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL
• Output frequency range: 10MHz to 150MHz
• VCO range: 240MHz to 500MHz
• Output skew: 200ps (maximum)
• Cycle-to-cycle jitter, (all banks ÷4): 55ps (maximum)
• Full 3.3V supply voltage
• -40°C to 85°C ambient operating temperature
• Compatible with PowerPC™and Pentium™Microprocessors
• Available in lead-free packages
Pin Assignment
39 38 37 36 35 34 33 32 31 30 29 28 27
FSEL_B1 40
26
FSEL_B0 41
25
FSEL_A1 42
24
FSEL_A0 43
23
QA3 44
22
V_DDO 45
QA2 46
87973I-147
21
20
GNDO 47
19
QA1 48
18
V_DDO 49
17
QA0 50
16
GNDO 51
15
VCO_SEL 52
14
1 2 3 4 5 6 7 8 9 10 11 12 13
FSEL_FB1
QSYNC
GNDO
QC0
VDDO
QC1
FSEL_C0
FSEL_C1
QC2
V_DDO
QC3
GNDO
INV_CLK
52-Lead, 10mm x 10mm LQFP
REVISION B 07/27/15
1
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