8745BI-21 Datasheet, PDF (1/20 Pages) Integrated Device Technology – 1:1 Differential-to-LVDS Zero Delay Clock Generator

1:1 Differential-to-LVDS Zero Delay
Clock Generator
8745BI-21
Datasheet
General Description
Features
The 8745BI-21 is a highly versatile 1:1 LVDS Clock Generator. The
8745BI-21 has a fully integrated PLL and can be configured as a
zero delay buffer, multiplier or divider, and has an output frequency
range of 31.25MHz to 700MHz. The Reference Divider, Feedback
Divider and Output Divider are each programmable, thereby
allowing for the following output-to-input frequency ratios: 8:1, 4:1,
2:1, 1:1, 1:2, 1:4, 1:8. The external feedback allows the device to
achieve “zero delay” between the input clock and the output clock.
The PLL_SEL pin can be used to bypass the PLL for system test and
debug purposes. In bypass mode, the reference clock is routed
around the PLL and into the internal output dividers.
Pin Assignments
CLK 1
nCLK 2
MR 3
nFB_IN 4
FB_IN 5
SEL2 6
VDDO 7
nQFB 8
QFB 9
GND 10
20 SEL1
19 SEL0
18 VDD
17 PLL_SEL
16 VDDA
15 SEL3
14 GND
13 Q
12 nQ
11 VDDO
8745BI-21
• One differential LVDS output designed to meet
or exceed the requirements of ANSI TIA/EIA-644
One differential feedback output pair
• Differential CLK, nCLK input pair
• CLKx, nCLKx pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
• Output frequency range: 31.25MHz to 700MHz
• Input frequency range: 31.25MHz to 700MHz
• VCO range: 250MHz to 700MHz
• External feedback for “zero delay” clock regeneration
with configurable frequencies
• Programmable dividers allow for the following output-to-input
frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8
• Cycle-to-cycle jitter: 30ps (maximum)
• Output skew: 40ps (maximum)
• Static phase offset: 25ps ± 125ps
• Full 3.3V supply voltage
• -40°C to 85°C ambient operating temperature
• Available in lead-free (RoHS 6) package
• For functional replacement part use 8T49N285
20-Lead SOIC
7.5mm x 12.8mm x 2.3mm package body
M Package
Top View
Block Diagram
PLL_SEL ^Pullup
Q
÷1, ÷2, ÷4, ÷8,
÷16, ÷32, ÷64
0
Q
CLK ^Pulldown
CLK ^Pullup
1
QFB
QFB
32 31 30 29 28 27 26 25
SEL0 1
24 GND
SEL1
nc
nc
CLK
nCLK
nc
2
ICS8745BI-21
23
ED ³ 32 Lead VFQFN ²²
S _{4 5mm x 5mm x 0.925mm 21}
PO ⁵
package body
20
O 6
K Package
19
PR ⁷
Top View
18
Q
nQ
VDDO
GND
QFB
nQFB
MR 8
17 VDDO
9 10 11 12 13 14 15 16
FB_IN ^Pulldown
FB_IN ^Pullup
SEL0 ^Pulldown
SEL1 ^Pulldown
SEL2 ^Pulldown
SEL3 ^Pulldown
MR ^Pulldown
PLL
8:1, 4:1, 2:1, 1:1,
1:2, 1:4, 1:8
©2017 Integrated Device Technology, Inc.
1
Revision E, January 10, 2017