8732-01 Datasheet, PDF (1/17 Pages) Integrated Device Technology – Low Voltage, Low Skew 3.3V LVPECL Clock Generator

Low Voltage, Low Skew
3.3V LVPECL Clock Generator
8732-01
Data Sheet
GENERAL DESCRIPTION
The 8732-01 is a low voltage, low skew, 3.3V LVPECL Clock
Generator. The 8732-01 has two selectable clock inputs. The
CLK0, nCLK0 pair can accept most standard differential input
levels. The single ended clock input accepts LVCMOS or LVTTL
input levels. The 8732-01 has a fully integrated PLL along with
frequency configurable outputs. An external feedbackinput and
outputs regenerate clocks with “zero delay”.
The 8732-01 has multiple divide select pins for each bank of
outputs along with 3 independent feedback divide select pins
allowing the 8732-01 to function both as a frequency multiplier
and divider. The PLL_SEL input can be usedto bypass the
PLL for test and system debug purposes.In bypass mode,
the input clock is routed around the PLLand into the internal
output dividers.
Features
• Ten differential 3.3V LVPECL outputs
• Selectable differential CLK0, nCLK0 or
LVCMOS/LVTTL CLK1 inputs
• CLK0, nCLK0 supports the following input types:
LVPECL, LVDS, LVHSTL, SSTL, HCSL
• CLK1 accepts the following input levels:
LVCMOS or LVTTL
• Maximum output frequency: 350MHz
• VCO range: 250MHz to 700MHz
• External feedback for “zero delay” clock regeneration
with configurable frequencies
• Cycle-to-cycle jitter: CLK0, nCLK0, 50ps (maximum)
CLK1, 80ps (maximum)
• Output skew: 150ps (maximum)
• Static phase offset: -150ps to 150ps
• Lead-Free package fully RoHS compliant
BLOCK DIAGRAM
PIN ASSIGNMENT
V_CCO
QA0
52 51 50 49 48 47 46 45 44 43 42 41 40
1
39
2
38
V_CCO
nQB3
nQA1
V_EE
PLL_SEL
V_CCO
nQA2
QA3
nQA3
V_EE
5
35
6
34
7
ICS8732-01
33
31
10
30
11
29
12
28
13
27
14 15 16 17 18 19 20 21 22 23 24 25 26
QB2
V_EE
MR
V_CCO
QB1
nQB0
QB0
V_EE
52-Lead LQFP
10mm x 10mm x 1.4mm package body
Y package
Top View
©2016 Integrated Device Technology, Inc
1
Revision E January 22, 2016